`timescale 1ns / 1ps				  
module Controller (Op,Func, AluOp, SrcASel,SrcBSel, ExtOp, JAL,JR,Branch,Jump, RegWrite, WriteToRD, Load, Store, MemSize, SignedLoad);
	input [5:0] Op,Func; //instruction
	output WriteToRD; //select which field in the determines the destination register
		//0 = bits 20-16 (rt) , 1= bits 15-11 (rd)
	output JAL;     	// Asserted on JAL, JALR
	output JR;			// Asserted on JR, JALR
	output Branch;		// Asserted on all branches
	output Jump;		// Asserted on all jumps
	output Load;	    //1 = Data from Memory goes to register, 0 = ALU output goes to register 
	output [1:0] AluOp; //which operation to perform in the ALU
	output [1:0] MemSize;	// 01 = byte, 10 = halfword, 11 = word
	output Store;
	output SignedLoad;  //1=memory read will be sign extended
	output SrcBSel;		//where to get data for the ALU operand B:  0=Reg2 or 0, 1=SE Immed
	output SrcASel;     //where to get data for the ALU operand A; 0=Reg1 or PC+4, 1=Immediate	
	output RegWrite;	//enable write to register file 
	output [1:0] ExtOp; //00 = ZeroExt, 01=SignExt, 10=Alignleft, 11=Get ShAmt
	
	wire op_special = (Op==0); //uses func codes
	wire op_j = (Op==2);
	wire op_jal = (Op==3);
	wire op_beq = (Op==4);
	wire op_bne = (Op==5);
	wire op_blez = (Op==6);
	wire op_bgtz = (Op==7);
	wire op_addi = (Op==8);
	wire op_addiu = (Op==9);
	wire op_slti = (Op==10);
	wire op_sltiu = (Op==11);
	wire op_andi = (Op==12);
	wire op_ori = (Op==13);
	wire op_xori = (Op==14);
	wire op_lui = (Op==15);
	wire op_lb = (Op==32);
	wire op_lh = (Op==33);
	wire op_lw = (Op==35);
	wire op_lbu = (Op==36);
	wire op_lhu = (Op==37);
	wire op_sb = (Op==40);
	wire op_sh = (Op==41);
	wire op_sw = (Op==43);
	
	//functions
	wire fn_sll = (Func==0);
	wire fn_srl = (Func==2);
	wire fn_sra = (Func==3);
	wire fn_sllv = (Func==4);
	wire fn_srlv = (Func==6);
	wire fn_srav = (Func==7);
	wire fn_jr = (Func==8);
	wire fn_jalr = (Func==9);
	wire fn_mfhi = (Func==16);
	wire fn_mthi = (Func==17);
	wire fn_mflo = (Func==18);
	wire fn_mtlo = (Func==19);
	wire fn_mult = (Func==24);
	wire fn_multu = (Func==25);
	wire fn_add = (Func==32);
	wire fn_addu = (Func==33);
	wire fn_sub = (Func==34);
	wire fn_subu = (Func==35);
	wire fn_and = (Func==36);
	wire fn_or = (Func==37);
	wire fn_xor = (Func==38);
	wire fn_nor = (Func==39);
	wire fn_slt = (Func==42);
	wire fn_sltu = (Func==43);

	// Make it work!
	
endmodule