//--------------------------------------------------------------------------------------------------
//
// Title       : registerfile
// Design      : Base Components
// Author      : Steven
// Company     : UW CSE
//
//-------------------------------------------------------------------------------------------------
//
// File        : mips_reg_file.v
// Generated   : Mon Mar 20 16:51:43 2006
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1 ns / 1 ps

module registerfile ( WriteData ,RegWrite ,WriteReg ,CLK, Data1 ,Data2 ,Read1 ,Read2 ) /* synthesis syn_black_box */ ;
	
	input [4:0] Read1,Read2,WriteReg; // the registers numbers to read or write
	input [31:0] WriteData; // data to write
	input RegWrite, // The write control
	CLK; // the clock to trigger write 
	wire WE = (RegWrite && (WriteReg !== 0));
	output [31:0] Data1, Data2; // the register values read
	parameter INIT_FILE="$DSN\\src\\register_init.hex";
	
	//synopsys translate_off
	
`ifndef SYNTHESIS
	
	reg [31:0] RF [31:0]; /* synthesis syn_ramstyle="registers" */ // 32 registers each 32 bits long
	assign Data1 = RF[Read1];
	assign Data2 = RF[Read2];
	// Initial Value File //
	

	initial begin
		$readmemh(INIT_FILE,RF);
	end
	
	always begin
			// write the register with new value if Regwrite is high
			@(posedge CLK) if (WE) RF[WriteReg] <= WriteData;
		end
`else
	wire [31:0] RO1, SPO, RO2;
	assign Data1 = RO1;
	assign Data2 = RO2;
	genvar i; // loop variable for generate statement
	generate 						
		for (i = 0; i < 32; i = i + 1) 
			begin:BIT

				`library("P0","ovi_unisim")
				`library("P1","ovi_unisim")
	
				
				RAM32X1D #(.INIT(32'h00000000)) P0 (.DPO(RO1[i]), // Port A 1-bit data output
				.SPO(SPO[i]), // Port B 1-bit data output
				.A0(WriteReg[0]), // Port A address[0] input bit
				.A1(WriteReg[1]), // Port A address[1] input bit
				.A2(WriteReg[2]), // Port A address[2] input bit
				.A3(WriteReg[3]), // Port A address[3] input bit
				.A4(WriteReg[4]), // Port A address[4] input bit
				.D(WriteData[i]), // Port A 1-bit data input
				.DPRA0(Read1[0]), // Port B address[0] input bit
				.DPRA1(Read1[1]), // Port B address[1] input bit
				.DPRA2(Read1[2]), // Port B address[2] input bit
				.DPRA3(Read1[3]), // Port B address[3] input bit
				.DPRA4(Read1[4]), // Port B address[4] input bit
				.WCLK(CLK), // Port A write clock input
				.WE(WE) // Port A write enable input
				); 

				RAM32X1D #(.INIT(32'h00000000)) P1 (.DPO(RO2[i]), // Port A 1-bit data output
				.SPO(SPO[i]), // Port B 1-bit data output
				.A0(WriteReg[0]), // Port A address[0] input bit
				.A1(WriteReg[1]), // Port A address[1] input bit
				.A2(WriteReg[2]), // Port A address[2] input bit
				.A3(WriteReg[3]), // Port A address[3] input bit
				.A4(WriteReg[4]), // Port A address[4] input bit
				.D(WriteData[i]), // Port A 1-bit data input
				.DPRA0(Read2[0]), // Port B address[0] input bit
				.DPRA1(Read2[1]), // Port B address[1] input bit
				.DPRA2(Read2[2]), // Port B address[2] input bit
				.DPRA3(Read2[3]), // Port B address[3] input bit
				.DPRA4(Read2[4]), // Port B address[4] input bit
				.WCLK(CLK), // Port A write clock input
				.WE(WE) // Port A write enable input
				); 
		end
	endgenerate
`endif

//synopsys translate_on

endmodule 

module registerfile2 ( WriteData ,RegWrite ,WriteReg ,CLK, Data1 ,Data2 ,Read1 ,Read2 ) /* synthesis syn_black_box */ ;
	
	input [4:0] Read1,Read2,WriteReg; // the registers numbers to read or write
	input [31:0] WriteData; // data to write
	input RegWrite, // The write control
	CLK; // the clock to trigger write 
	wire WE = (RegWrite && (WriteReg !== 0));
	output [31:0] Data1, Data2; // the register values read
	parameter INIT_FILE="$DSN\\src\\register_init.hex";
	
	//synopsys translate_off
	
	wire WriteThru1 = ((WE) && (WriteReg == Read1));
	wire WriteThru2 = ((WE) && (WriteReg == Read2));
`ifndef SYNTHESIS
	reg [31:0] RF [31:0]; /* synthesis syn_ramstyle="registers" */ // 32 registers each 32 bits long
	// Initial Value File //

	assign Data1 = (WriteThru1)? WriteData : RF[Read1];
	assign Data2 = (WriteThru2)? WriteData : RF[Read2];


	initial begin
		$readmemh(INIT_FILE,RF);
	end
	
	always begin
			// write the register with new value if Regwrite is high
			@(posedge CLK) if (WE) RF[WriteReg] <= WriteData;
		end
`else
	wire [31:0] SPO,RO1,RO2;
	assign Data1 = (WriteThru1)? WriteData : RO1;
	assign Data2 = (WriteThru2)? WriteData : RO2;
	genvar i; // loop variable for generate statement
	generate 						
		for (i = 0; i < 32; i = i + 1) 
			begin:BIT

				`library("P0","ovi_unisim")
				`library("P1","ovi_unisim")

				
				RAM32X1D #(.INIT(32'h00000000)) P0 (.DPO(RO1[i]), // Port A 1-bit data output
				.SPO(SPO[i]), // Port B 1-bit data output
				.A0(WriteReg[0]), // Port A address[0] input bit
				.A1(WriteReg[1]), // Port A address[1] input bit
				.A2(WriteReg[2]), // Port A address[2] input bit
				.A3(WriteReg[3]), // Port A address[3] input bit
				.A4(WriteReg[4]), // Port A address[4] input bit
				.D(WriteData[i]), // Port A 1-bit data input
				.DPRA0(Read1[0]), // Port B address[0] input bit
				.DPRA1(Read1[1]), // Port B address[1] input bit
				.DPRA2(Read1[2]), // Port B address[2] input bit
				.DPRA3(Read1[3]), // Port B address[3] input bit
				.DPRA4(Read1[4]), // Port B address[4] input bit
				.WCLK(CLK), // Port A write clock input
				.WE(WE) // Port A write enable input
				); 

				RAM32X1D #(.INIT(32'h00000000)) P1 (.DPO(RO2[i]), // Port A 1-bit data output
				.SPO(SPO[i]), // Port B 1-bit data output
				.A0(WriteReg[0]), // Port A address[0] input bit
				.A1(WriteReg[1]), // Port A address[1] input bit
				.A2(WriteReg[2]), // Port A address[2] input bit
				.A3(WriteReg[3]), // Port A address[3] input bit
				.A4(WriteReg[4]), // Port A address[4] input bit
				.D(WriteData[i]), // Port A 1-bit data input
				.DPRA0(Read2[0]), // Port B address[0] input bit
				.DPRA1(Read2[1]), // Port B address[1] input bit
				.DPRA2(Read2[2]), // Port B address[2] input bit
				.DPRA3(Read2[3]), // Port B address[3] input bit
				.DPRA4(Read2[4]), // Port B address[4] input bit
				.WCLK(CLK), // Port A write clock input
				.WE(WE) // Port A write enable input
				); 
		end
	endgenerate
`endif

//synopsys translate_on
endmodule