This calendar represents my intentions. Reality trumps intention, should the two disagree.

Key:

Exam

Holiday

Homework

Lecture

Section

Week of	Monday	Wednesday	Thursday	Friday
January 3	Introduction Slides Moore's Law (1975!) Chapter 1 HW0 out	The MIPS R2000 ISA: Basics of the ISA: registers, memory, simple instructions Sections 2.1-2.3, 2.5-2.6 Realize A.10 exists HW1 out- Assembly and Machine Language Programming	Memory and Data Representations Section notes Sections 3.7, 2.8	The MIPS R2000 ISA: Instruction Encoding Example code Section 2.4
January 10	Other Addressing Modes Simple Assembler Programming Section 2.9, A.5 Examples from class	More on Assembler Programs Examples from class HW1 due (Revised) HW2 out- Programming w/ Cebollita (Revised)	Tools and the Operating Environment HW2, Parts 1 and 2	Procedure calls Chapters 2.7, A.6 Lecture notes
January 17	MLK Day	Procedure calls Chapters 2.7, A.6 Lecture notes	Compiling / Assembling / Linking / Loading Typechecking & Memory Safety Sections 2.10, A.1-A.4	Mid-term Review
January 24	Midterm I Answer key Distribution of Grades HW2 due (Revised) HW3 out - Intro to Machine Design (w/ SMOK) (Revised)	Intro to Datapaths Intro to SMOK Chapters 5.1-5.3	Compiler Optimization Performance Sections 4.1-4.3	Midterm Review
January 31	Single-cycle implementation: datapath Chapter 5.4 HW3 due HW4 out - Single-cycle MIPS implementation	Single-cycle: control Chapters 5.4, Appendix C.2 Stack machine example	CISC Machines Chapter 3.12, skim VAX ISA	The OS: Exceptions and Simple Address Translation Chapters 5.6, Appendix A.7
February 7	Exceptions / Address Translation / IO Controllers (cont.) Exceptions, Protection, and the OS Chapters 5.6, Appendix A.7	Exceptions / Address Translation / IO Controllers (cont. II) Exceptions, Protection, and the OS Chapters 5.6, Appendix A.7 HW4 due HW5 out - MIPS + OS	HW5	Multi-cycle     Chapters 5.5 Pipelining: Introduction     Chapter 6.1
February 14	Pipelining: Data path Chapters 6.2, 6.3	JJGZ Day	Pipelining Pipelining exercises out	Pipelining: Data Hazards Chapters 6.4, 6.5
February 21	Presidents Day	Pipelining: Control Hazards Chapter 6.6 HW5 due	Pipelining Midterm prep Pipelining exercises due	Branch Prediction Exceptions Chapter 6.8
February 28	Midterm II Answer key Distribution of Grades	Caches I Chapters 7.1, 7.2 HW6 out - Caching	0.5% of C++ 2.5% of Visual Studio 50% of cvs	Caches II Chapters 7.2, 7.3
March 7	Virtual memory I Chapters 7.4	Virtual memory II Chapters 7.4	TBD	(Micro)Architectures: Early 1990's Mips R4000, PowerPC (601), Pentium HW6 due
March 14	Final Exam 8:30-10:20 Distribution of Grades