HW6 Task 4 - Implement a Cache

Supplement to the hw6 main assignment.

1. Implement the Base Cache Organization

Okay, finally we're ready to implement the caches. As mentioned over and over already, you do this via the C++ that implements the ICache and DCache component types. We'll begin by making (and implementing) the following cache organization (for both the I- and D- caches):

• direct-mapped
• 32 lines
• one word lines (i.e., 4 data bytes per line)
• write-allocate (DCache)
• write-through (DCache)

We'll explore other variations for the cache organizations as part of Task 5.

We'll use a simple, approximate formula for the time penalty of a cache miss, measured in processor cycles:

miss penalty =     1          /* send address to memory */
                 + 4          /* memory latency */
                 + linesize   /* linesize is measured in words -- time to xfer data */

For example, with the cache organization above a cache miss entails 5 stall cycles, with the data being produced on the sixth cycle.

Note: This formula is only an approximation, chosen in part so that when you run your SMOK simulations they finish in reasonable time. (The real time required to run them is roughly linear in the simulated cache miss penalty.)

Modify ICache.cpp to implement the cache described above. (Since no writes occur to that cache, this is relatively simple.) Modify DCache.cpp as well. Make sure you include the final bit of implementation required for the flush instruction as you do this.

Your code should acquire statistics such as the number of reads requested, the number of writes, the read hit rate, and the write hit rate. These should be dumped to a file on termination. The skeletal code has a skeletal implementation of this, with the code that actually writes to the file being insidethe destructor methods.

2. Run the Benchmark and Record Statistics

Run the benchmark you created in Task 3. Record statistics on the machine's performance using this simple cache organization.