Final Exam Topics

Preface

There exam period is 110 minutes long. The exam will be targetted at around 70 minutes.

Some questions will be oriented towards the assignments - they'll be about ideas or activities done there. I haven't tried to enumerate the assignment-related material separately from the list of topics below, though.

As a guide to studying, there are two distinct questions you might ask yourself about each topic: what, and why. By "what" I mean understanding what how something works, and by "why" I mean, "Why is it done this way? What is the goal that we're trying to achieve? Why isn't some other way of try How does it fit into the larger picture of building a system?"

Questions, especially of the "why" variety, often will span topics.

Topics

I'm organizing this list by chapter in the text. You should also review the course lecture schedule - not all topics are covered adequately in the text. (A list of non-text topics appears at the end.) Note that the meaning of the items on this list are open to interpretation, so it would be a mistake to completely suspend your own judgement about what the list should be. (It should be all the material covered in lectures, sections, and assignments.)

Chapter 2

defining equation for performance
CPI
benchmark suites

Chapter 3

data representations
ISA
RISC & load-store architecture (vs. CISC)
registers
instruction operation types: arithmetic, logical, load/store, test, branch, jump
addressing modes
instruction encoding
procedure calls and use of the stack
compiling: going from a higher level language (e.g., C) to assembler
assembling
linking
instruction, static data, (heap,) and stack
exceptions/interrupts/traps
(Some of this, especially the last few, is in Appendix A.)

Chapter 4

floating point representation
(binary integer arithmetic, and hex, are assumed from CSE 370)

Chapter 5

single-cycle datapath and control
multi-cycle datapath (and the basics of control)
exceptions

Chapter 6

pipelining
dependences: RAW, WAR, and WAW.
hazards
exceptions
branch prediction
(superscalar and super-pipelining)

Chapter 7

memory hierarchy: registers / L1 / L2... / RAM (/ Disk)
cache organizations: fully associative, direct mapped, set-associative
demand load
write-through vs. write-back
address translation
virtual memory: page tables, TLB, page faults, TLB misses
memory protection

Chapter 8

polled vs. DMA IO (We didn't cover this chapter, but this idea came up in the projects. The block device controller is DMA -- it transfers into/out of memory directly. The character controller is polled -- instructions executed on the CPU are necessary to move each character in or out.)

Other

Pentium, PowerPC 601, Pentium 4, PowerPC G5/970
superscalar
dependences: WAW and WAR, in particular
register renaming
out of order execution / in order completion
simultaneous multithreading (aka hyperthreading) vs. multiple processors on a chip
branch target buffers

Basic execution of the OS
libraries
syscall's