More Notes About Pipeline Forwarding

Load Instructions

Instruction Fetch (IF)

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Instruction Decode (ID)

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Execute (EX)

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Memory (MEM)

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Write Back (WB)

Loads produce "new" values at the MEM stage. The MEM/WB -> EX forwarding only handles instructions which have distance 2 e.g. a load followed by an independent instruction and then an instruction dependent on the load. If there is a dependent instruction following a load, the pipeline must stall for one cycle. The effect is to force the dependent instruction to wait until the forwarded value is ready. See the figure on page 491 of the textbook.

Loads followed by a dependent store are a special case. If the destination of load is the register the store instruction is writing to memory, then an extra forwarding path MEM/WB -> MEM will eliminate the hazard. See page 488 of the textbook for more details.

Branch and Jump Instructions

Since the decision to take or not take the branch is not resolved until the EX stage, the pipeline has to stall two cycles. The delayed branch strategy always executes the instructions following the branch, so NOPs must be inserted by the compiler or the programmer if there are no available instructions to be executed.

For jump register instructions, the branch target is already known by the end of the ID stage but we treat these instructions the same way as other branches. This makes implementation easier.

It is possible to move the branch direction resolution to the ID stage. To gain one less cycle in branch latency, the target address must also be calculated in the same stage.