Brief Notes About Pipeline Forwarding

The standard five stage MIPS pipeline is:

Instruction Fetch (IF)

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Instruction Decode (ID)

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Execute (EX)

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Memory (MEM)

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Write Back (WB)

Remember that between each pair of adjacent pipeline stages is a set of registers which are named for the stages they separate. For example the registers between the EX and the MEM stages are called the EX/MEM pipeline register.

"New" values, that is ones which are not already in the register file, are produced in the the processor pipeline in two locations. These locations are the EX and MEM stages. These new values are not written to the register file until the WB stage. Since the registers are read in the ID stage, this leaves a window of three cycles for which old incorrect values are flowing through the pipeline. Forwarding can help cure this problem.

Consider the case of only arithmetic instructions. The only place new values are produced in this case is the EX stage. Forwarding will then take care of the following situations (forwarded registers are in bold):

Forwarding from/to Pipeline		Distance between Instructions
Register	Stage		Note	Example
EX/MEM	EX	1		addi $t0, $0, 1 subi $t1, $t0, 2
MEM/WB	EX	2	The forwarding occurs from the MEM/WB pipeline register because values have flowed down the pipeline. The value coming from the EX/MEM pipeline register is for the instruction following the one requiring forwarding.	addi $t0, $0, 1 andi $t1, $t2, 2 subi $t2, $t0, 2
"Register file"		3	See below	addi $t0, $0, 1 andi $t1, $t2, 2 slt $t2, $t4, $t5 subi $t3, $t0, 2

Instruction distance is calculated by subtracting instruction numbers, which are the addresses divided by four. Remember, instructions are word aligned. Alternatively you can subtract the instruction addresses then divide by four.

The "register file forwarding" is not implemented in the MIPS as true forwarding, that is a bus (group of wires) which travels from a pipeline register to a previous stage. The MIPS writes to the register file in the first half of a clock cycle and reads from the register file in the second half.

Due to a limitation in the SMOK simulator, you will need to implement "register file forwarding" literally. Newly written results will have to go around the register file and replace the values from the registers being read in the same cycle if the register numbers match.

Note it is possible to get two forwarded values for a single register. The most recently produced result has precedence and is in bold. The other forwarded value which is not used is in italics.

subi $t0, $0, 1
andi $t0, $t2, 2
slt $t2, $t0, $t5

In this case the result for $t0 from the andi instruction is used over the result from the subi instruction. The subi and andi instructions exhibit an output dependency. There is no hazard (Write After Write - WAW) in the pipeline, since instructions are executed in the same order as in the program. This may not be the case for all processors though but it is true for the MIPS processor you are studying.