6502 -> SLOOP Instruction Translation. Last revision: $Id: isa-trans.txt,v 1.6 2001/01/19 21:17:47 dugan Exp $ ------------------------------------------------------------------------- Introduction: This document details the translation of the 6502 instruction set into SLOOP instructions. Typically, each 6502 instruction will translate in a small sequence of SLOOP instructions. Once this translation has been taken place, pipelining techniques may be used to efficiently execute the resulting instruction stream. This document assumes that the reader is familiar with the SLOOP ISA. ------------------------------------------------------------------------- Notation and Assumptions: The 6502 fetch unit must fetch at least 3 bytes from the program memory. For notational convenience, we assume that these 3 bytes are made available to the translation unit using the following notation: op Opcode ; the first byte fetched ibu Immediate byte unsigned ; the second byte, not sign extended ibs Immediate byte signed ; the second byte, sign extended iw Immediate word ; the 2nd and 3rd bytes ibu, ibs, and iw are all 16 bit quantities. The difference between ibu and ibs is just that ibs is sign extended when expanded to a 16-bit entity. We make few assumptions about how the fetch unit operates. Either the datapath to memory can be widened to 24 bits, or the 6502 fetch unit may operate asynchronously with the SLOOP core. When enough data from the 6502 stream has been fetched (ie. the above quantities are all available) the translation unit can proceed. The translation unit will inform the fetch unit of how many bytes have been consumed, so that the fetch unit will know where to get the next 6502 instruction from. Below we will also use 6502 notation for addressing modes: Notation: Meaning: Size (bytes): ----------------------------------------------------------------- A accumulator #im immediate 2 zp zero-page 2 zp,X zero-page indexed 2 a absolute 3 (a) absolute indirect 3 a,X absolute indexed (X register) 3 a,Y absolute indexed (Y register) 3 (zp),Y indirect indexed 2 (zp,X) indexed indirect 2 Note that in most cases, much of the data required for an operation is already available in the result of the 3-byte 6502 fetch. If the operation is on immediate data, it has already been fetched, so the translation is trivial. If the operation requires that its operand be fetched, in many cases we have already fetched the required base (or absolute) address. In these cases, all that remains is to load the operand and then operate upon it. The most complicated addressing modes are those that require several fetches to get the operand. These include the absolute indirect and indirect indexed modes. In order to represent the translations more compactly, they are grouped to the extent possible. Many classes of operations differ only in the "fundamental" SLOOP operation needed to implement it. They all share the same "setup" code, which usually boils down to a sequence of loads required to get the operand. 6502 Instruction Sloop Instruction ----------------------------------- ADC ADD/ADDI SBC SUB/SUBI AND AND/ANDI EOR XOR/XORI ORA OR/ORI CMP CMP 6502 Instuction(s) Addr mode SLOOP sequence ---------------------------------------------------------------- ADC/SBC/AND/ imm XXXI sm, $RA, $RA, ibs EOR/ORA/CMP ------------------------------------------ zp LD 0, $RT, ibu($R0) XXX sm, $RA, $RA, $RT ------------------------------------------ abs LD 0, $RT, iw($R0) XXX sm, $RA, $RA, $RT ------------------------------------------ abs,x LD 0, $RT, iw($RX) XXX sm, $RA, $RA, $RT ------------------------------------------ abs,y LD 0, $RT, iw($RY) XXX sm, $RA, $RA, $RT ------------------------------------------ zp,y LD 0, $RT, ibu($RY) XXX sm, $RA, $RA, $RT ------------------------------------------ (zp,x) LD 0, $RT, ibu($RX) LD 0, $RT, 0($RT) XXX sm, $RA, $RA, $RT ------------------------------------------ (zp),y LD 0, $RT, ibu($R0) ADD 0, $RT, $RT, $RY LD 0, $RT, 0($RT) XXX sm, $RA, $RA, $RT ---------------------------------------------------------------- ASL/LSR/ROL/ROR accum XXX sm, $RA, $RA, $RA ------------------------------------------ abs LD 0, $RT, iw($R0) XXX sm, $RT, $RT, $RT ST 0, $RT, iw($R0) ------------------------------------------ zp LD 0, $RT, ibu($R0) XXX sm, $RT, $RT, $RT ST 0, $RT, ibu($R0) ------------------------------------------ a,x LD 0, $RT, iw($RX) XXX sm, $RT, $RT, $RT ST 0, $RT, iw($RX) ------------------------------------------ zp,y LD 0, $RT, ibu($R0) XXX sm, $RT, $RT, $RT ST 0, $RT, iw($R0) ---------------------------------------------------------------- INC/DEC accum XXX sm, $RA, $RA, $RA ------------------------------------------ abs LD 0, $RT, iw($R0) XXXI sm, $RT, $RT, 1 ST 0, $RT, iw($R0) ------------------------------------------ zp LD 0, $RT, ibu($R0) XXXI sm, $RT, $RT, 1 ST 0, $RT, ibu($R0) ------------------------------------------ a,x LD 0, $RT, iw($RX) XXXI sm, $RT, $RT, 1 ST 0, $RT, iw($RX) ------------------------------------------ zp,y LD 0, $RT, ibu($R0) XXXI sm, $RT, $RT, 1 ST 0, $RT, iw($R0) ---------------------------------------------------------------- INX/INY/DEX/DEY register XXXI sm, $RX/Y, $RX/Y, 1 ---------------------------------------------------------------- BCC relative BEQZ 0, 0x ---------------------------------------------------------------- BCS relative BEQZ 0, 0x ---------------------------------------------------------------- BEQ (z=1) relative BNEZ 0x02 ---------------------------------------------------------------- BNE (z=0) relative BEQZ 0x02 ---------------------------------------------------------------- BMI (n=1) relative BNEZ 0x80 ---------------------------------------------------------------- BPL (n=0) relative BEQZ 0x80 ---------------------------------------------------------------- BRA (always) relative BEQZ 0x00 ---------------------------------------------------------------- BVS (v=1) relative BNEZ 0x40 ---------------------------------------------------------------- BVC (v=0) relative BEQZ 0x40 ---------------------------------------------------------------- BCS (c=1) relative BNEZ 0x01 ---------------------------------------------------------------- BCC (c=0) relative BEQZ 0x01 ---------------------------------------------------------------- CLC ANDI $RP, $RP, 0xFE ---------------------------------------------------------------- CLD ANDI $RP, $RP, 0xF7 ---------------------------------------------------------------- CLI ANDI $RP, $RP, 0xFB ---------------------------------------------------------------- CLV ANDI $RP, $RP, 0xFE ---------------------------------------------------------------- SEC ORI $RP, $RP, 0x01 ---------------------------------------------------------------- SED ORI $RP, $RP, 0x08 ---------------------------------------------------------------- SEI ORI $RP, $RP, 0x04 ---------------------------------------------------------------- CPX/CPY imm XXXI sm, $RT, $RX/Y, ibs ------------------------------------------ abs LD 0, $RT, iw($R0) XXX sm, $RT, $RT, $RX/Y ------------------------------------------ zp LD 0, $RT, ibu($R0) XXX sm, $RT, $RT, $RX/Y ---------------------------------------------------------------- LDA/LDX/LDY imm ADDI sm, $RA/X/Y, $R0, ibs ---------------------------------------------------------------- LDA/LDX/LDY/ abs LD/ST sm, $RA/X/Y, iw($R0) STA/STX/STY ------------------------------------------ zp LD/ST sm, $RA/X/Y, ibu($R0) ------------------------------------------ (zp),y LD 0, $RT, ibu($R0) ADD 0, $RT, $RY, $RT LD/ST sm, $RA, 0($RT) ------------------------------------------ (zp,x) LD 0, $RT, ibu($RX) LD/ST sm, $RA, 0($RT) ------------------------------------------ zp,x LD/ST sm, $RA/X/Y, ibu($RX) ------------------------------------------ zp,y LD/ST sm, $RA/X/Y, ibu($RY) ------------------------------------------ abs,x LD/ST sm, $RA/X/Y, iw($RX) ------------------------------------------ abs,y LD/ST sm, $RA/X/Y, iw($RY) ---------------------------------------------------------------- NOP NOP ---------------------------------------------------------------- BIT These look at the accumulator, and set status flags. We can implement them with AND and the approppriate mask) ---------------------------------------------------------------- PHA/PHP/PHX/PHY/ Push onto the stack. Implement with: SUBI 0, $SP, $SP, 1 ST 0, $RA/$RP/$RX/$RY, 0($RS) ---------------------------------------------------------------- PLA/PLP/PLX/PLY Pull from the stack. Implement with: LD/ST 0, $RA/$RP/$RX/$RY, 0($RS) ADDI 0, $SP, $SP, 1 ---------------------------------------------------------------- TAX/TAY/TSX/ TXA/TXS/TYA Register transfer instructions. Can all be implemented with ADD. ADD 0, $RA/X/S/Y, $RA/X/S/Y, $R0 ---------------------------------------------------------------- JMP abs J iw ------------------------------------------ (abs) LD $RT, iw($R0) JR $RT ---------------------------------------------------------------- JSR abs STW $RPC, -1($RS) ADDI $RS, $RS, -2 J iw ---------------------------------------------------------------- RTS LDW $RT, 1($RS) ADDI $RS, $RS, 2 JR $RT ---------------------------------------------------------------- BRK not implemented yet. ---------------------------------------------------------------- RTI not implemented yet. ----------------------------------------------------------------