Cache Simulator Experiments and Writeup
I'd like you to run the following experiments with your simulator. I
want you to run each experiment with the following file: l100000.2
(the SECOND large reference trace from lisp -- it's important you use
this one, as it is much more interesting than the first!!).
- Impact of linesize for writethrough caches: Examine the
effect of varying line size. Run the WriteThrough simulator (no
write-buffer) with linesizes of 4, 8, 16, 32, and 64 bytes. (The
total cache size should always be fixed at 8192 bytes!). This is a
total of 5 runs.
- Impact of linesize for writeback caches: Repeat the above,
but with the writeback cache (again, no write-buffer). (This is a
total of 5 more runs.)
- Impact of write-buffer depth:Now, pick the parameter set
from above which gave you the best results (use minimum stall cycles,
NOT miss rate as your metric!), and using those settings, experiment
with write-buffer depth. Run the simulator with write-buffer depths
of 1, 2, 4, and 8. (This is 4 more runs.)
- Impact of cache size:Again, chosing the parameter set
from the above that gave you best results (write buffer size,
write policy, line size) experiment with total cache size.
Try sizes of 2048, 4196, 8192, 16384, and 32768 bytes.
(This is 5 more runs (actually 4 because you already have the
data for 8192)).
The above looks like a lot of work, but it's really pretty mechanical.
It should just be a matter of changing some constants in your program,
recompiling, and running it on the right input. You and your partner
can divide the work, so it shouldn't take more than an hour or so to
get these numbers.
The Writeup
We'd like you to turn in a writeup which contains the following information
- Changes. A high-level description (a couple of sentences is fine)
of what you needed to change in the code to get the writethrough
cache, the write-buffer, and the writeback policy working.
- 7 graphs:
- Impact of linesize for writethrough caches: We'd like 2
graphs, one showing miss rate vs. linesize, the other showing stall
cycles per instruction vs. linesize.
- Impact of linesize for writeback caches:Same as above.
- Impact of total cache size:Same as above.
- Impact of write-buffer depth:Just one graph, showing
stall cycles per instruction vs. write-buffer depth.
Be sure to show us the baseline (no
write-buffer) information as well.
- Extra credit. If you did any extra credit, tell us what you did and
how you did it (high-level descriptions please). Also, if you ran
any experiments to study the impact of your enhancements, tell us about them.