Machine Organization & Assembly Language

CSE 378, Spring Quarter 2000

Superscalar Architecture

Issue multiple instructions on each clock cycle.

CPI is less than one!

A MIPS datapath allowing an ALU op or a branch, and a load or store, to be executed simultaneously is shown below:

There is an additional read port on the instruction memory, two more read and one more write port on the register file and another ALU.

This additional ALU only handles address calculations for loads and stores.

If the next two instructions to be executed don't conform to the constraint mentioned before, we only execute the first instruction. The hardware does this check.

Obviously this limits what instructions can be executed simultanously.

Further problems arise from data and control hazards. The key is that only independent instructions can be executed simultanously.

One solution is Simultaneous Multi-threading. Executing instructions from different programs guarantees independence... up to a point.

What about coordination (synchronization) between programs? Separate programs need separate registers... 32 is not enough!

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