CSE378 -- Spring 2000

Programming Assignment #5


Trace-driven simulation is a widely used technique to assess the performance of a memory hierarchy. In this assignment you will write a SPIM program for a skeleton trace-driven simulator to assess a D-cache.

A trace-driven simulator generally operates as follows:





Your assignment is to write a single level D-cache simulator in SPIM. The trace will consist of a sequence of memory references in the format <operation><address> where operation is "1" for read and "2" for write, and address is a 32-bit byte address. The sequence is terminated by 0 0. Assume that the total sequence is no more than 1024 references (pairs). The cache will be 128 blocks with a block size of 8 bytes. It uses write back, write-allocate and LRU replacement. (The tiny cache size is used because with such a short reference stream a larger cache would be mostly compulsory misses.) Your output, displayed on the SPIM console, will be

You will be given a test sequence soon. It is recommended that for debugging you make an even smaller cache and trace.