CSE378 -- Spring 2000

CSE378 -- Spring 2000

Programming Assignment #5

Trace-driven simulation is a widely used technique to assess the performance of a memory hierarchy. In this assignment you will write a SPIM program for a skeleton trace-driven simulator to assess a D-cache.

A trace-driven simulator generally operates as follows:

Input:

A trace, i.e. a sequence of memory references

One or more cache descriptions with type, size, associativity, block size, replacement algorithm, etc. and their organization into a hierarchy.

A write policy.

Access times for the various components of the memory hierarchy.

Output:

A set of statistics such as hit ratio, miss ratio, average memory access time, etc.

Cycles spent waiting at the various levels of the memory hierarchy, etc.

Algorithm:

Process each memory reference, decomposing the address into its (tag, index, displacement) components.

Check if the memory reference hits in the appropriate cache. (No data is actually stored; the simulation simply keeps track of which blocks are present.)

Take appropriate actions. In case of a hit, record statistics, possibly set dirty bits, etc. In the case of a miss, "bring in" the missing block, replace an old one, record statistics, etc.

Assignment

Your assignment is to write a single level D-cache simulator in SPIM. The trace will consist of a sequence of memory references in the format <operation><address> where operation is "1" for read and "2" for write, and address is a 32-bit byte address. The sequence is terminated by 0 0. Assume that the total sequence is no more than 1024 references (pairs). The cache will be 128 blocks with a block size of 8 bytes. It uses write back, write-allocate and LRU replacement. (The tiny cache size is used because with such a short reference stream a larger cache would be mostly compulsory misses.) Your output, displayed on the SPIM console, will be

The number of data references processed
The number of hits in the D cache.
The number of blocks written back.

You will be given a test sequence soon. It is recommended that for debugging you make an even smaller cache and trace.