1. Assume the "usual" 5-step pipeline design, give a longest instruction sequence illustrating a "data hazard" caused by computation of a single value.

2. How is a data hazard detected in hardware? Explain.

3. How can data hazards be reduced or eliminated in hardware? Explain.

4. If there were no hardware to detect and eliminate data hazards, how would it be done in software? What are the benefits/liabilities of solving data hazards in software?

5. What is a branch hazard? What are the options for handling it?

6. I/O device interrupts are handled more easily in a pipeline than arithmetic exceptions, e.g. overflow, because ...

7. What are temporal- and spatial-locality? Why are they so important?

8. In a cache what is the tag?

9. Consider a tight loop of 8 instructions that is executed 2^20 times, and containing a data hazard. Suppose there is an 8 word direct-mapped I-cache. What is the performance cost for this program of handling data hazards in software, assuming a miss penalty of 10 instruction times.

10. Writing a word to a cache is somewhat different depending on whether the cache is one word or several words wide. Explain the difference.

11. Miss Rate is not the star of a western novel, but ...

12. Caches have width and depth ... which helps temporal locality and which helps spatial locality?

13. What is the difference between early restart and requested word first?

14. Given a machine with a 15 cycle miss penalty, and a program with a 4% I-miss rate, an 8% D-miss rate, and 25% of the instructions reference D-memory, how much faster is the machine if the clock rate is doubled, given that CPI=3?

15. Give the steps in computing a physical address from a virtual address.

16. What information must a page table contain?

17. Argue that LRU is unrealistic by explaining what would be required to implement it for paging. Hint: Add a word to each page table entry to be a time stamp.

18. The opposite of write through is ... How does it work?

19. Why add page table bits, e.g. dirty bits, to the TLB?

20. Draw the schematic for a 32-bit ALU with AND, OR, ADD, SUB, SLT.

21. On a page fault, how does the OS know what location caused the fault?

22. The book reports typical TLB miss rates .01%-1%. Why so low?

23. The opposite of direct mapped is ... Give an example where it's used.

24. Will a 2-way or 4-way s. a. cache "conflict miss" less?

25. MIPS has 3 instruction formats and 5 addressing modes. What are they?

26. How many bits are required for a 1K cache of 32 byte blocks, assuming 2-way s.a. and 32-bit addresses.

27. What information must be known about an application and a computer to figure CPI?

28. How many bits is the significand field for IEEE 64-bit floating point?

29. Using Figure 5.29, label the green control lines with the values they must have to implement (a) subi, (b) lw, (c) sw, (d) beq (e) jal.

30. Explain the differences between multi-cycle and pipelined datapaths.

31. Describe the contents of the ID/EX pipeline register.

32. What is the strangest term used in computer architecture?