The Problem with Miss-rate
It doesn't tell the whole story:
Consider increasing direct-mapped cache from 32K to 64K
Miss Rate drops from 5% to 4%. If the larger cache implies a cycle time of 18ns and the smaller cache implies a cycle time of 15ns, the smaller cache machine has better performace
Postulate: CPI w/o stalls is unchanged Miss penalty 180ns Memory references per instruction = 1.5
CPU Time = (CPU execution clock cycles + Memory-stall clock cycles) ? Clock cycle time