Logic of Memory Reference for 3100

Virtual address

TLB access

TLB Hit?

No

Write Protect

Exception

Cache

Hit?

Deliver data

to CPU

TLB miss

interrupt

No

Yes

Yes

Yes

No

Try to read data

from cache

Cache miss stall

4

Write data into cache,

update the tag, and put

the data and the address

into the write buffer.

Write

Access

Bit=1

Write ?

Yes

No

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