Handling Misses
The processor has to stall the instruction that missed; instruction misses stall the pipeline at IF while data misses stall in MEM.
Operations by controller on a miss:
1. Compute PC-4
2. Access address in main memory and wait for completion.
3. Move data to cache, write tag bits, set Valid.
4. Restart execution pipeline at the fetch for instruction misses, or MEM for data misses.