Delayed Branches
Make the control hazard an architectural feature
The instruction following a branch is always executed
The compiler or assembler has to find an instruction to fill this slot
- If none can be found, a NOP has to be inserted
The instructions scheduled into the delay slot must
- EITHER always be executed whether the branch is taken or not
- OR have no side-effects
Less popular now since longer pipelines and multiple instruction issue mean the single delay slot does not help as much
Dynamic predictors have increased in popularity as transistor density has increased