Control Signals
Signal Effect Deasserted Effect Asserted
MemRead None Contents at address read out
MemWrite None Contents at address replaced
ALUSelA PC is first ALU operand Reg is first ALU operand
RegDst Reg Destination from rt Reg Destination from rd
RegWrite None Contents of reg replaced
MemtoReg Data to reg from ALU Data to reg from memory
IorD Mem Address from PC Mem Addr from ALU
IRWrite None Value from memory to IR
PCWrite None PC is written
PCWriteCond None PC is written if Zero asserted