/* Test bench for isPrime sequential circuit */
module isPrime_tb ();

  // define parameters (input width and clock period)
  parameter T = 20, W = 4;

  // define module port connections
  logic clk;
  logic [W-1:0] Num;
  logic P;
  logic Start, Reset;
  logic Ready, Done;
  
  // instantiate module
  isPrime #(W) dut (.*);
  
  // create simulated clock
  initial begin
    clk <= 0;
    forever #(T/2) clk <= ~clk;
  end  // clock initial
  
  integer i;
  initial begin
    Reset = 1; Start = 0;  @(posedge clk);
    Reset = 0;             @(posedge clk);
    for (i = 0; i < 2**W; i++) begin
      Start = 1; Num = i; @(posedge clk);
      Start = 0;          @(posedge Ready);
      $display("T = %4t, isPrime(%2d) = %s",
               $time, Num, P ? "Yes" : "No ");
    end
    @(posedge clk);
    $stop();
  end  // initial
  
endmodule  // isPrime_tb