module isPrime_datapath #(parameter W=4)
                        (input  logic clk,
                         input  logic [W-1:0] Num,
                         output logic P,
                         output logic N_lt_3, NmodF_zero, F_gt_halfN,
                         input  logic Load_regs, Special, Clr_P, Set_P, Incr_F);

  // internal datapath signals and registers
  logic [W-1:0] F;  // current factor
  logic [W-1:0] N;  // copy of Num
  
  // datapath logic
  always_ff @(posedge clk) begin
    if (Load_regs)  begin
      F <= 2;
      N <= Num;
    end
    if (Incr_F)   F <= F + 1'b1;
    if (Special)  P <= (N == 2);
    if (Clr_P)    P <= 1'b0;
    if (Set_P)    P <= 1'b1;
  end
  
  // output assignments
  assign N_lt_3     = (N < 3);
  assign NmodF_zero = (N % F == 0);
  assign F_gt_halfN = (F > N/2);
  
endmodule  // isPrime_datapath