module isPrime_control (input  logic clk, Start, Reset,
                        output logic Ready, Done,
                        input  logic N_lt_3, NmodF_zero, F_gt_halfN,
                        output logic Load_regs, Special, Clr_P, Set_P, Incr_F);

  // define state names and variables
  enum {S_idle, S_check, S_done} ps, ns;
  
  // controller logic w/synchronous reset
  always_ff @(posedge clk)
    if (Reset)
      ps <= S_idle;
    else
      ps <= ns;
  
  // next state logic
  always_comb
    case (ps)
      S_idle:  ns = Start ? S_check : S_idle;
      S_check:  ns = (N_lt_3 | NmodF_zero | F_gt_halfN) ? S_done : S_check;
      S_done:  ns = Start ? S_done : S_idle;
    endcase
  
  // output assignments
  assign Ready     = (ps == S_idle);
  assign Done      = (ps == S_done);
  assign Load_regs = (ps == S_idle) & Start;
  assign Special   = (ps == S_check) & N_lt_3;
  assign Clr_P     = (ps == S_check) & ~N_lt_3 & NmodF_zero;
  assign Set_P     = (ps == S_check) & ~N_lt_3 & ~NmodF_zero & F_gt_halfN;
  assign Incr_F    = (ps == S_check) & ~N_lt_3 & ~NmodF_zero & ~F_gt_halfN;
  
endmodule  // isPrime_control