module isPrime #(parameter W=4)
               (input  logic clk,
                input  logic [W-1:0] Num,
                output logic P,
                input  logic Start, Reset,
                output logic Ready, Done);
  
  // define status and control signals
  logic N_lt_3, NmodF_zero, F_gt_halfN;
  logic Load_regs, Special, Incr_F, Clr_P, Set_P;
  
  // instantiate control and datapath
  isPrime_control c_unit (.*);
  isPrime_datapath #(W) d_unit (.*);
  
endmodule  // isPrime