/* Test bench for sequential binary multiplier with separate add and shift
 * stages.
 */
module mult_testbench();

  parameter WIDTH = 4, T = 20;

  // define ports
  logic [2*WIDTH-1:0] product;
  logic Ready, Done;
  logic clk, Start, reset;
  logic [WIDTH-1:0] multiplicand, multiplier;
  
  mult #(WIDTH) dut (.*);

  initial begin
    clk <= 0;
    forever #(T/2) clk <= ~clk;
  end  // clock initial
  
  initial begin
    multiplicand = 'd14; multiplier = 'd11;
    Start = 0; reset = 1; #(T)
    reset = 0; #(T)
    Start = 1; #(T)
    Start = 0;
    repeat (2**4)  #(T);
    $stop;
  end  // initial

endmodule  // mult_testbench