module mult_datapath #(parameter WIDTH=8)
                     (product, Q, P, multiplicand, multiplier, clk,
                      Load_regs, Shift_regs, Add_regs, Decr_P);

  // port definitions
  output logic [2*WIDTH-1:0] product;
  output logic [WIDTH-1:0] Q, P;  // note: unnecessary bits for P (could use $clog2)
  input  logic [WIDTH-1:0] multiplicand, multiplier;
  input  logic clk, Load_regs, Shift_regs, Add_regs, Decr_P;
  
  // internal logic
  logic C;
  logic [WIDTH-1:0] A, B;

  // assignments
  assign product = {A, Q};
  
  // datapath logic
  always_ff @(posedge clk) begin
    if (Load_regs) begin
      A <= 0;
      C <= 0;
      B <= multiplicand;
      Q <= multiplier;
      P <= WIDTH;
    end
    if (Decr_P)           P <= P - 1;
    if (Add_regs)         {C, A} <= A + B;
    else if (Shift_regs)  {C, A, Q} <= {C, A, Q} >> 1;
  end  // always_ff
  
endmodule  // mult_datapath