module mult_control (Q0, P_zero, clk, reset, Start, Ready, Done,
                     Load_regs, Shift_regs, Add_regs, Decr_P);

  // port definitions
  input  logic Q0, P_zero, clk, reset, Start;
  output logic Ready, Done, Load_regs, Shift_regs, Add_regs, Decr_P;
  
  // define state names and variables
  enum {S_idle, S_add, S_shift, S_done} ps, ns;
  
  // controller logic w/synchronous reset
  always_ff @(posedge clk)
    if (reset)
      ps <= S_idle;
    else
      ps <= ns;
  
  // next state logic
  always_comb
    case (ps)
      S_idle:  ns = Start ? S_add : S_idle;
      S_add:   ns = S_shift;
      S_shift: ns = P_zero ? S_done : S_add;
      S_done:  ns = S_idle;
    endcase
  
  // output assignments
  assign Ready = (ps == S_idle);
  assign Done = (ps == S_done);
  assign Load_regs = (ps == S_idle) & Start;
  assign Shift_regs = (ps == S_shift);
  assign Add_regs = (ps == S_add) & Q0;
  assign Decr_P = (ps == S_add);
  
endmodule  // mult_control