/* Sequential binary multiplier with separate add and shift stages.
 * When Ready, takes a Start signal and then computes the product of two data
 * inputs of width WIDTH over 2*WIDTH clock cycles before asserting Done.
 * See Lecture 7 for controller and datapath design.
 */
module mult #(parameter WIDTH=8)
            (product, Ready, Done,
             clk, Start, reset, multiplicand, multiplier);

  // port definitions
  output logic [2*WIDTH-1:0] product;
  output logic Ready, Done;
  input  logic clk, Start, reset;
  input  logic [WIDTH-1:0] multiplicand, multiplier;
  
  // define status and control signals
  logic Load_regs, Shift_regs, Add_regs, Decr_P;
  logic [WIDTH-1:0] Q, P;  // unnecessary bits for P
  logic Q0, P_zero;
  assign Q0 = Q[0];
  assign P_zero = (P == 0);
  
  // instantiate control and datapath
  mult_control c_unit (.*);
  mult_datapath #(WIDTH) d_unit (.*);

endmodule  // mult