// Test bench for Design Example #1 (arbitrary)
module top_level_tb();
  
  parameter T = 20;
  
  logic [3:0] A;
  logic E, F;
  logic clk, Start, reset_b;
  
  top_level dut (.*);

  initial begin
    clk <= 0;
    forever #(T/2) clk <= ~clk;
  end  // clock initial
  
  initial begin
    Start = 0;  reset_b = 0;  @(posedge clk);
                reset_b = 1;  @(posedge clk);
    Start = 1;                @(posedge clk);
    Start = 0;
    repeat (2**4)             @(posedge clk);
    $stop;
  end  // initial
  
endmodule  // top_level_tb