// Implementation of Design Example #1 (arbitrary)
module top_level (A, E, F, clk, Start, reset_b);

  // port definitions
  output logic [3:0] A;
  output logic E, F;
  input  logic clk, Start, reset_b;
  
  // internal signals
  logic set_E, clr_E, set_F, clr_A_F, incr_A;
  
  // instantiate controller and datapath
  controller c_unit (.set_E, .clr_E, .set_F,
                     .clr_A_F, .incr_A, .A2(A[2]),
                     .A3(A[3]), .Start, .clk,
                     .reset_b);
  datapath d_unit (.*);
  
endmodule  // top_level