// Datapath module for Design Example #1 (arbitrary)
module datapath (A, E, F, clk, set_E, clr_E, set_F,
                 clr_A_F, incr_A);
  
  // port definitions
  output logic [3:0] A;
  output logic E, F;
  input  logic clk, set_E, clr_E, set_F, clr_A_F, incr_A;
  
  // datapath logic
  always_ff @(posedge clk) begin
    if (clr_E)       E <= 1'b0;
    else if (set_E)  E <= 1'b1;
    if (clr_A_F) begin
      A <= 4'h0;
      F <= 1'b0;
    end
    else if (set_F)  F <= 1'b1;
    if (incr_A)      A <= A + 4'h1;
  end  // always_ff
  
endmodule  // datapath