// test bench for synchronous single-port RAM
module RAM_single_tb ();

  parameter D=8, A=4, T=20;

  logic clk, wren;
  logic [A-1:0] addr;
  logic [D-1:0] din, dout;

  RAM_single #(D, A) dut(.*);

  initial begin
    clk <= 0;
    forever #(T/2) clk <= ~clk;
  end  // clock initial

  int i;
  initial begin
    wren = 1;
    for (i = 0; i < 2**A; i++) begin
      addr = i; din = 2**A-1 - i; @(posedge clk);
    end  // for
    wren = 0;
    for (i = 0; i < 2**A; i++) begin
      addr = i; din = i; @(posedge clk);
    end  // for
    @(posedge clk);
    $stop;
  end  // initial

endmodule  // RAM_single_tb