module ROM_tb();

  logic [3:0] addr;
  logic [6:0] data1, data2;

  ROM_case dut1(.addr, .data(data1));
  ROM_file dut2(.addr, .data(data2));

  int i;
  initial begin
    for (i = 0; i < 2**4; i++) begin
      addr = i; #10;
    end  // for
    $stop;
  end  // initial

endmodule  // ROM_tb