/* String manipulator FSM test bench */
module fsm_tb();

  logic clk, reset, in, out;
  
  fsm dut (.*);
  
  // simulated clock
  parameter period = 100;
  initial begin
    clk <= 0;
    forever
      #(period/2)
      clk <= ~clk;
  end  // initial clock

  initial begin
      reset <= 1; in <= 0; @(posedge clk);
      reset <= 0; in <= 0; @(posedge clk);
                  in <= 0; @(posedge clk);
                  in <= 1; @(posedge clk);  // one 1 in a row
                  in <= 0; @(posedge clk);
                  in <= 1; @(posedge clk);  // two 1's in a row
                  in <= 1; @(posedge clk);
                  in <= 0; @(posedge clk);
                  in <= 1; @(posedge clk);  // four 1's in a row
                  in <= 1; @(posedge clk);
                  in <= 1; @(posedge clk);
                           @(posedge clk);
    $stop;  // end simulation
  end  // initial signals
  
endmodule  // fsm_tb