/* threeOnes_testbench runs through all transitions of the threeOnes FSM
 * after a reset pulse by inputting a 0 after strings of 1's of increasing
 * length from 1 to 4. detect should only go high after the string of 3 1's
 * and twice at the end of the string of 4 1's.
 */
module threeOnes_tb();
  logic clk, reset, w;
  logic detect;

  threeOnes dut (.*);

  // Set up the clock
  parameter T = 20;  // clock period
  initial begin
      clk <= 0;
    forever #(T/2) clk <= ~clk;
  end

  // Set up the inputs to the design. Each line is a clock cycle.
  initial begin
    reset <= 1;          @(posedge clk);
    reset <= 0; w <= 0;  @(posedge clk);
                         @(posedge clk);
                w <= 1;  @(posedge clk);  // one 1
                w <= 0;  @(posedge clk);
                w <= 1;  @(posedge clk);  // two 1's
                         @(posedge clk);
                w <= 0;  @(posedge clk);
                w <= 1;  @(posedge clk);  // three 1's
    repeat (2)           @(posedge clk);
                w <= 0;  @(posedge clk);
                w <= 1;  @(posedge clk);  // four 1's (outputs two 1's)
    repeat (3)           @(posedge clk);
                w <= 0;  @(posedge clk);
    repeat (2)           @(posedge clk);

    $stop; // End the simulation
  end
endmodule  // threeOnes_tb