/* Testbench for DE1_SoC that does the exact same thing as threeOnes_tb:
 * Runs through all transitions of the threeOnes FSM
 * after a reset pulse by inputting a 0 after strings of 1's of increasing
 * length from 1 to 4. detect should only go high after the string of 3 1's
 * and twice at the end of the string of 4 1's.
 */
module DE1_SoC_tb ();

  // define signals
  logic       CLOCK_50;
  logic [9:0] LEDR;
  logic [3:0] KEY;

  // define parameters
  parameter T = 20;

  // instantiate module
  DE1_SoC dut (.*);

  // define simulated clock
  initial begin
    CLOCK_50 <= 0;
    forever  #(T/2)  CLOCK_50 <= ~CLOCK_50;
  end

  // define testbench signals
  initial begin
    KEY <= 4'hF;  @(posedge CLOCK_50);  // start unpressed
    KEY[3] <= 0;  @(posedge CLOCK_50);
    KEY[3] <= 1;  @(posedge CLOCK_50);
                  @(posedge CLOCK_50);
                  @(posedge CLOCK_50);
    KEY[0] <= 0;  @(posedge CLOCK_50);  // one 1
    KEY[0] <= 1;  @(posedge CLOCK_50);
    KEY[0] <= 0;  @(posedge CLOCK_50);  // two 1's
                  @(posedge CLOCK_50);
    KEY[0] <= 1;  @(posedge CLOCK_50);
    KEY[0] <= 0;  @(posedge CLOCK_50);  // three 1's
    repeat (2)    @(posedge CLOCK_50);
    KEY[0] <= 1;  @(posedge CLOCK_50);
    KEY[0] <= 0;  @(posedge CLOCK_50);  // four 1's (outputs two 1's)
    repeat (3)    @(posedge CLOCK_50);
    KEY[0] <= 1;  @(posedge CLOCK_50);
    repeat (2)    @(posedge CLOCK_50);
                  @(posedge CLOCK_50);
    $stop;
  end

endmodule  // DE1_SoC_tb