/* Top-level module for DE1-SoC hardware connections to implement a threeOnes FSM.
 *
 * The inputs are connected to pushbuttons (reset - KEY3, w - KEY0).
 * Clock shown on LEDR1 and w shown on LEDR2. (skipping LEDR0 for doc cam view)
 * The output is connected to LEDR3.
 */
module DE1_SoC (CLOCK_50, KEY, LEDR);

  input  logic     CLOCK_50;  // 50MHz clock
  output logic [9:0] LEDR;
  input  logic [3:0] KEY;      // low when pressed

  // Generate clk off of CLOCK_50, whichClock picks rate
  parameter whichClk = 25;
  logic [31:0] divided_clocks;
  //clock_divider cdiv (.clock(CLOCK_50), .divided_clocks);
  logic clk;
  //assign clk = divided_clocks[whichClk];
  assign clk = CLOCK_50;
  assign LEDR[1] = clk;        // show clock signal on LEDR1

  // Generate submodule input and output signals
  logic  reset, w, detect;
  assign reset   = ~KEY[3];    // KEYs are active low
  assign w       = ~KEY[0];
  assign LEDR[2] = w;        // show w signal on LEDR2
  assign LEDR[3] = detect;    // show detect signal on LEDR3

  // instantiate submodules
  threeOnes FSM (.*);

endmodule  // DE1_SoC