// Control module for Design Example #1 (arbitrary)
module controller (set_E, clr_E, set_F, clr_A_F, incr_A,
						 A2, A3, Start, clk, reset_b);
						 
   // port definitions
	input  logic Start, clk, reset_b, A2, A3;
	output logic set_E, clr_E, set_F, clr_A_F, incr_A;
	
   // define state names and variables
	enum logic [1:0] {S_idle, S_1, S_2 = 2'b11} ps, ns;

	// controller logic w/synchronous reset
	always_ff @(posedge clk)
		if (~reset_b)
			ps <= S_idle;
		else
			ps <= ns;
			
	// next state logic
	always_comb
		case (ps)
			S_idle:	ns = Start ? S_1 : S_idle;
			S_1:		ns = (A2 & A3)	? S_2 : S_1;
			S_2:		ns = S_idle;
		endcase
		
	// output assignments
	assign set_E =   (ps == S_1) & A2;
	assign clr_E =   (ps == S_1) & ~A2;
	assign set_F =   (ps == S_2);
	assign clr_A_F = (ps == S_idle) & Start;
	assign incr_A =  (ps == S_1);
	
endmodule  // controller