// Parameterized, synchronous single-port RAM module
module RAM_single #(parameter D=8, A=4)
                  (input  logic clk, wren,
						 input  logic [A-1:0] addr,
						 input  logic [D-1:0] din,
						 output logic [D-1:0] dout);

	logic [D-1:0] RAM [0:2**A-1];

	// uncomment to initialize RAM in simulation (need to modify path to file)
	//initial
		// reads hex values from file into array
		//$readmemh("C:/371/lec4/ramdata.txt", RAM);

	always_ff @(posedge clk) begin
		if (wren) begin
			RAM[addr] <= din;
			dout <= din;
		end
		else
			dout <= RAM[addr];
	end  // always_ff

endmodule  // RAM_single