Synario tips from previous quarters


Right. If you try to run the tutorial included in Synario Help, you'll
find some problems such as the one you described. The problem is, Synario
(or at least the the tutorial) is not designed to work under the NT
protected filesystem. It tries to create a file in a directory in which
you don't have access permissions, so it fails. Try the tutorial that we
put in the 370 Web page. Let me know if you run into any problem.


On Mon, 20 Oct 1997, Leo Lai wrote:

> Young,
> I assume that you are accessing the tutorial from Synario Help
> menu, pdf format, right. I got the same error when I tried it. There is
> a another tutorial for Synario that you can access from the 370 web page,
> and personally, I think that one is much better.
> > Hi. I was just doing the tutorial in the NT lab. When I got to
> > the 10th page or so on the tutorial, it told me to open the file "top.sch"
> > or something like that by double clicking on it. Then I've got a
> > following error.
> >
> > Schematic Editor MajorError
> >
> > ! Failed to create Log file V:~_SC150AA.TMP
> >
> Leo

RE: Synario (fwd)

Miguel Figueroa (
Thu, 23 Oct 1997 09:28:34 -0700 (PDT)

Hi all,

This is the reply I got from the guys at support. Please let me (them)
know if you have any problems running Synario on any machine other than


---------- Forwarded message ----------
Date: Thu, 23 Oct 1997 09:18:57 -0700
From: Aaron Wood <>
To: 'Miguel Figueroa' <>
Cc: support <>
Subject: RE: Synario

We've have seen problems with PML10 not being able to connect to
Synario. We're looking into it right now. That's all that has been
reported to support. If you see problems with any other PC's in the PML
lab let us know by stating witch PML machine is the culprit.


Aaron Wood
CSL Support

> -----Original Message-----
> From: Miguel Figueroa []
> Sent: Wednesday, October 22, 1997 6:04 PM
> To: support@cs
> Subject: Synario
> Hi,
> I'm the TA for CSE370. We're using Synario in the current homework,
> and
> I've got many complaints from students saying that they can't run the
> software on particular machines (they haven't specified which ones,
> though). I understand that Synario has a hardware key protection or
> something like that. Could you tell me exactly in which machines the
> software runs? Can they use any machine in the 232 lab? In any other
> lab?
> Thanks for your help,
> Miguel Figueroa

If you are not NT person like me...

Arun Somani (
Wed, 12 Mar 1997 08:59:46 -0800

Since we are doing a group project in CSE370, you may need to share your
files with your partner (and partner only). Many of you have already
figured it out. In case you have not, I got two helpful messages,
one from Justin Miller and other from Renee Reed which I am including
to help you out.

This is quite easy with NT. First create
a subdirectory in their home dir. Then
use the properties option on the file menu
in NT Explorer and select security. Add
the user names for whoever they wish to
share with and choose the appropriate permissions.

An alternative is for you to send me the members
of each group and we set up a shared dir in the
project area. This would require a day to
complete on our end. Students would be responsible
for moving a copy to their home dir if they
want to keep the files after the end of quarter
as we would be deleting the project area after


Yes, students can do it on their own.

1) Find the directory that your project will be in. Right click on the
directory and select "Properties".

2) Select the "Security" tab, then click the "Permissions" button.

3) Once the "Directory Permissions" window is open, click the "Add"
button. Once the "Add Users and Groups" windows appears, click the
"Show Users" button.

4) Select the user whom you wish to give access privileges. Hit "OK" to
return to the "Directory Permissions" screen.

5) Highlight the user you have just added. Under the "Type of Access:"
menu, use the "Special Directory Access..." and "Special File Access..."
commands to customize the access privileges.

6) When opening the project in Synario with only the single folder
accessible, the full path of the project's directory must be typed in,
or else the message "You do not have permission to open this directory"
will appear.

That's it! If you think it's appropriate, please forward this to the
class mailing list.

-Justin and Carl

Lab problems and other good stuff

Matt Lease (
Wed, 22 Jan 1997 20:30:48 -0800 (PST)

Support may have already answered this, but if not:

There have been several problems in the lab related to a shortage of disk
space on the local hard drives. This can prevent NT from being able to
log you on, prevent a file from being opened, or prevent
you from using the binary.ini fix for Synario (trying to copying it to
C:\temp when there's no room for it). The hard drives are cleaned of
excess files by selecting "Clean up and restart" from the start menu, and
this was done on (hopefully) all machines in Sieg 232.

If you nevertheless run into this problem while logged on, please use this
option to get rid of the garbage on the local disk. If you cannot log on
to a specific machine (and it is because of the "unable to create profile"
error), log on to a different machine and send mail to support@cs so they
can take care of it.

For future reference:
Please let us (cse370-ta@cs) and support@cs know IMMEDIATELY when you have
what seems to be a bug related problem; we can't help you unless we know
about it, and the sooner we know about it the sooner we can find a
work-around for it and make others aware of it. Problems are
going to arise inevitably this quarter in the lab; Synario was already
buggy last quarter and on top of that we now have a recently
installed new operating system. Complaining to your
classmates is not going to fix this; this is the environment you are going
to have to work in, so the best thing you can do is accept it and try to
make the best of it. Jaya and I are here to help you, so hopefully during
lab hours and via the generic web site you can make use of our familiarity
with Synario.

As a final note:
The generic web site is still very small as the project began only 2 and a
half weeks ago, but hopefully as it grows it can be a resource to you for
answering questions which might arise in the lab. If you have any
comments regarding adding specific content / improving it, please feel
free to email suggestions to me or Jaya.


> > I'm also wondering a little about the stability of the NT machines.
> > Today, they wouldn't let me log on because they couldn't create a
> > temporary profile directory (or some such, I've sent mail to support@cs).
> > A week ago, I tried starting Synario to begin exploring it, but none of
> > the entries on the Start menu pointed to anything. Also about a week ago,
> > MS Word wouldn't open my homework file because there wasn't enough disk
> > space available for its temporary files. I'm willing to accept that I've
> > been unusually unlucky ... but if my experiences are common, we can expect
> > to have a lot of problems this quarter.
> >
> >
> > Scott.
> > ------------- End Forwarded Message -------------
> >
> >


quick lab tip

Matt Lease (
Fri, 21 Feb 1997 20:20:15 -0800 (PST)

If you are creating multiple instances of an ABEL submodule and want to
use one alias name to refer to all of them, you must use "," notation and not
".." notation when you declare the alias. For example, if X3..X0 are your
submodule instances, your alias MUST look like:

xAlias = [X3,X2,X1,X0];

and NOT

xAlias = [X3..X0];

Creating an alias declaration for submodules is the only case (we know
of) in which "," notation and ".." notation cannot be used interchanably.

Hope this helps!

Matt Lease
Undergraduate, University of Washington Department of Computer Science

Current Project(s):
Digital Design Online Resources

Hex in verilog.

Jason Gurule (
Sun, 11 May 1997 21:05:33 -0700 (PDT)

For those who would rather put in hex numbers in verilog you
before the number. Example:
is f5. I haven't tried this, but it is in the verilog help file.

Jason Gurule


Comments in Verilog

Matt Lease (
Wed, 5 Mar 1997 22:29:17 -0800 (PST)

C++ style ('//')

> How do you denote comments in a Verilog Test Fixture?

flipflops in ABEL

Matt Lease (
Mon, 10 Mar 1997 20:47:47 -0800 (PST)

> When I am trying to do my mode selector, I try to use the flip-flops
> provided by the ABEL (istype 'reg, buffer';) However, when I am doing
> that, I have no idea how can I set the initial value for that signal. I
> try the .PR, .SP and something like that and I still get the undefined
> signal. Is there any ways to do the preset with the provided flip-flops
> in the ABEL?

Here is a pretty complete description of using flip-flops in ABEL:

instantiation: "istype 'reg, buffer'"
assignment: "flipFlopName := VALUE"
synchonous reset: "flipFlopName.clr = rst", where "rst" is your input pin
that indicates when you want to reset to 0
synchonous set: "flipFlopName.set = set", where "set" is you input pin
that indicates when you want to set the value to 1
Use the synchonous output in your calculations (ie check what your current
state is if you have a flip-flops representing your FSM's current state)
: somePin = flipFlopName.fb;

.clr, .set, and .fb should be the only .extensions you use

You should not say: "somepin = flipFlopName", as this is ambiguous whether
you want the synchronous or asynchonous output of the flip-flop. Always
use the .fb extension to specifiy the synchonous output.

HOpe this helps. Any questions? Let me know.

addition in ABEL

Gaetano Borriello (gaetano)
Fri, 8 Nov 1996 11:57:36 -0800

Some notes on addition in ABEL (to reiterate and clarify what was said in
lecture today):

To add two numbers that are 4 bits wide:



	C = A + B;   "will yield the correct result
	[CO, C] = A + B;   "will not work because the sizes do not match
	[CO, C] = [0, A] + [0, B]   "will have the desired effect as we 
                                    "want to make sure to are added 0s to 
                                    "the carry-out

	C = A + B + CI;   "will not work as CI will be sign-extended 
                          "to be [CI,CI,CI,CI] 
	C = A + B + [0,0,0,CI]  "will work as intended

To add numbers that have different widths:


	D = A + B;   "will not work
	D = [0,0,A] + [0,0,B];   "will only work for unsigned numbers
	D = [A[3],A[3],A] + [B[3],B[3],B];   "has proper sign-extension 

	D[4:0] = [0,A] + [0,B];   "will add the four-bit values and save the 
                                  "carry out in D[4] 

Block Symbols

Jayapriya Srinivasan (
Tue, 4 Feb 1997 15:26:39 -0800 (PST)

There is a link now in the Generic Home page on how to Create block
symbols and use them in the higher level schematic.


Jayapriya Srinivasan :)

Re: Alarm clock display

Arun Somani (
Wed, 12 Mar 1997 09:03:00 -0800

My intend was that if you are in reading mode (like new value for AL1, AL2,
Timer, and clock) then you should be displaying shifter data. Otherwise
clock data. You may add other stuff in that like show AL1 or AL2 or timer etc.
by including additional control signals.

> We have a question about the "Clock Display" module on the data path
> diagram you provided. We can see that the two inputs to the mux are the
> normal clock and the output from the 4-bit parallel shift register. We
> are a little confused about the origin of the "SD" input. Is the purpose
> of this mux to display any new input (for any non-clock mode), as opposed
> to the normal clock readout? Thanks for the help.

inary.INI problem (contd)

Jayapriya Srinivasan (
Fri, 14 Mar 1997 15:22:48 -0800 (PST)

Larry and I were working on this problem and he says that creating a new
project automatically loads up the Binary.INI file. Therefore whenever you
get the error message "Binary.INI not found.." then
1)Create a new project
2)import your source files
This should rectify the problem. If it doen't then it means that in your
profile a system variable called temp is not set and you need to send mail
to support about this . At this point you should try running synario on a
diffrent machine.

LArry said he would talk to support about this.
Sorry to all for any inconvinience caused by this problem.


declaring bus as part of interface

Arun Somani (
Fri, 14 Mar 1997 17:23:02 -0800

My experts tell me that it is seemingly not possible
to do it. So continue with interface(x15..x0,......) kind of declaration.

Good luck.


Tip for HW #4/Synario

Corin Anderson (
Tue, 22 Oct 1996 17:45:48 -0700 (PDT)

Tip #1:
Don't start the names of any of your files with a number, like
4_bit.syn. Synario doesn't like this, a lot. It expresses its
anger with you by saying Failed! when you try to simulate the
circuit. This leads to...

Tip #2:
In the simulator window, if you get the cryptic Failed! message,
you can review what's happened by selecting the View Log... item
from the File menu. Scroll down until you see the section with
the error message.


P.S. If you're curious about tip #1, I beleive it's because Synario uses
the names of files for some internal variables, and thus parses the names
of files just like C variables.

synario file names

Gaetano Borriello (gaetano)
Thu, 31 Oct 1996 00:44:38 -0800

It seems that some of the problems that some of you have been
experiencing are related to the consistency of the names of files
and symbols that synario expects.

Here are some rules to try to follow.

Give unique root names to all .abl and .sch files.

Give the same root name to all .tf files and symbols that
are based on a corresponding .abl or .sch file.

It appears to be especially important to give symbols the
same name as the .abl or .sch file that they are
based on.

I hope these guidelines help. As always, let me know of problems
you can't resolve easily and see the web announcements for details
of how to change protections so that I can see the files in question.



"does not fit"

Gaetano Borriello (gaetano)
Thu, 21 Nov 1996 13:02:13 -0800

Some of you are getting a message that your counter design (exercise 4,
assignment 7) does not fit into a E0320 PLD. Clearly, this is ridiculous
because the equations generated by Synario from you ABEL description are
quite simple and certainly less than 8 product terms each (the limit of
this PLD).

The problem is related to how you are specifying the value of the current
state of a flip-flop. Lets say we have a flip-flop in our design
defined by the statement:

foo pin istype 'reg,buffer';

When we want to specify the value that foo should store at the next clock
edge we say:

foo := 1;

When we want to use the current value of the flip-flop we say:

x = foo.fb;

Note that this is different than:

x = foo;

which is the value of the pin of the PLD.

This is different because there are two ways in which the value of a
flip-flop can be fed back into the AND-array of this PLD (see the
E0320 map): one right from the output of the FF, and another from
the pin of the chip. Note that these are not the same signal as
there is a tri-state buffer between them. However, you'll notice
that both these feedbacks go through the same multiplexer and onto
a single wire back into the AND-array. Clearly, I can only configure
the PLD to use one of these, not both. So, if my specification uses
foo.fb and foo on the right side of an equation or in the test
condition of a WHEN clause then I can't fit the design into this
PLD (because of "too many feedbacks").

The solution is to be consistent and always use xxx.fb or xxx in
your logic and never both. I would recommend you use xxx.fb as this
makes the design more portable to other devices that may not have
feedback directly from a pin.


reserved keywords

Gaetano Borriello (gaetano)
Fri, 22 Nov 1996 16:34:15 -0800

Here is a more or less complete list of reserved keywords. Try very hard not
to use these in naming signals or modules. In some cases, they could work,
but don't count on it. I hope this will eliminate some time-consuming

	always		and		assign		attribute
	begin		buf		bufif0		bufif1
	case		casex		casez		cmos
	deassign	default		defparam	disable
	edge		else		end		endattribute
	endcase		endfunction	endmodule	endprimitive
	endspecify	endtable	endtask		event
	for		force		forever		fork
	function	highz0		highz1		if
	ifnone		initial		inout		input
	integer		join		large		macromodule
	medium		module		nand		negedge
	nmos		nor		not		notif0
	notif1		or		output		parameter
	pmos		posedge		primitive	pull0
	pull1		pulldown	pullup		rcmos
	real		realtime	reg		release
	repeat		rnmos		rpmos		rtran
	rtranif0	rtranif1	scalared	signed
	small		specify		specparam	strength
	strong0		strong1		supply0		supply1
	table		task		time		tran
	tranif0		tranif1		tri		tri0
	tri1		triand		trior		trireg
	unsigned	vectored	wait		wand
	weak0		weak1		while		wire
	wor		xnor		xor

zero1 and zero2

Gaetano Borriello (gaetano)
Mon, 9 Dec 1996 11:06:39 -0800

For the purposes of this assignment, you can combine zero1 and zero2 in
a separate AND gate from your PLD so that you can save 1 input.

Implement the AND gate in a separate .abl or .sch file.

Re: PR 6

John Alexander (
Tue, 26 Nov 1996 14:52:03 -0800 (PST)

Do it on a transition from a >35 state if change exists.

On Mon, 25 Nov 1996, Leif Krichoff wrote:
> Anyone have any ideas on how to do a seperate state equation in ABEL to
> dispence the coins?


bug in Synario printing

Gaetano Borriello (gaetano)
Fri, 6 Dec 1996 12:51:25 -0800

Some or all of you will probably run into a bug that John Alexander uncovered
recently. The bug manifests itself when you try to print a long waveform that
spans more than one page AND that waveform includes busses.

Basically, the Synario printing routines do not do the right thing with bus
values at the page breaks. Specifically, they drop the values of the busses
completely and either print a horizontal line (looks like tri-state) or
nothing at all. Sometimes they fold over other parts of the waveform making
a mess of the waveform.

There are two ways to fix this. The bad and simple way is not to use busses
at all. The better but more annoying way is to print the pages one at a
time (for example, to print a waveform from 0-500ns that spans five pages,
we would first print 0-100 on a single page, then 100-200 on another page,
etc.) This will generate five separate 1-of-1 sheets rather than five 1-of-5
partial waveforms. To do this kind of hand-crafted page breaking, you can
use the dialog box that appears when you print from the waveform viewer window.

Thanks again for you patience.

Tue Nov 26 14:52:11 1996 PST" --


Synario Tips

Mat Martineau (
Mon, 12 Jan 1998 16:32:32 -0800 (PST)


Reading this message carefully will save you many hours of frustration.

I promise.

Here are a few hints on how to keep Synario happy:


1. Be patient. The Project Navigator window (the first one that comes up

when you load Synario) coordinates between all of the other programs, like

the Schematic and Text editors. Whenever you change one of your source

files, the Project Navigator rebuilds some files and reorganizes them.



*** Never do anything until the status bar at the bottom of the Project

*** Navigator says "Ready" or "Hierarchy Up To Date"!!!

*** (or something to that effect)



Don't close windows. Don't save anything. Don't print anything. Just

wait. If you can't see the Project Navigator window, wait until the mouse

cursor stops changing, then wait a few more seconds.


2. Never start your filenames with numbers. Synario uses lots of

temporary files, and starting your filename with a number confuses it when

it tries to name certain temp files. It takes more work than you think to

re-name everything.



3. If Synario does freeze, here is what you do:

* Hit Control-Alt-Delete (it won't reboot the computer in NT)

* Click the "Task Manager" button on the window that pops up.

* Click the "Applications" tab in the Task Manager window.

* There should be an entry that says "Synario - Not Responding"

Click on it, then click the "End Task" button. After a few

seconds, another window will pop up asking if you want to

wait - just click the "End Task" button on that window.

Synario should go away.

* Log off, then log back on and try again.

(if you know UNIX, I have "ps" and "kill" programs for the NT command

line that do the job faster. I'll put them in the class directory.)


4. Put different projects in different directories. Things tend to get

cluttered if you don't. If you want to copy a project to a new directory,

use "Save As" in the Project Navigator - it will take care of copying all

of your source files too.


5. If odd things start happening with your project, try using "Clean Up

All" in the Project Navigator File menu. It will get rid of all of the

temporary files. If that doesn't work, create a new project and import

your source files into that new project.


6. The "BINARY.INI" problem when loading Synario: Run "Clean Up and

Restart" from the Start button menu.


7. Don't forget rule 1! Synario will crash frequently if you do things

too fast.


Send me mail or visit my office hours if you have any problems.




final project

Bob Alverson (
Mon, 2 Jun 1997 22:14:33 -0700

1. Will be due in class Friday.

2. You should be able to map your design into 3 EO600's or better.

3. How do you get it to map? One way:

a. Look at the reduced equations. If there are any with
more than 8 product terms, try to combine some terms.
Don't cares are the easiest way to do this.

b. Once all equations need 8 terms or less, partition
the outputs into groups of size small enough to fit
with the inputs,states, and internal nodes needed.

c. Split up design into a version for each group. Map
each piece. Write a "glue" ABEL-HDL file to presetn
provide the original interface to proc.abl, using
the new split files.

d. Make sure your processor still runs.

4. I did not remember the I/O's quite right. The EO600 can have
upto 16 outputs and 21 total inputs+outputs+states+nodes. The
extra input is for an extra clock *only*.



Re: control.abl

Bob Alverson (
Fri, 30 May 1997 09:02:26 PDT

> This might be an error. In the control module ABEL file there is an alias
> for LOAD and I think the last two bits are swaped. It should be
> LOAD = [1,0,0,0,0,0,1,0]
> I am comparing it to the assignment handout and also in the dmem32 module.

The control.abl file should have LOAD defined as above. The
dmem32.abl file is the master definition of instruction encodings.


Re: Output Waveforms

Miguel Figueroa (
Wed, 5 Nov 1997 17:30:51 -0800 (PST)

It is OK. Since there are no delay specifications on ABEL code, your final
simulation doesn't show any delay behavior. If you'd like to see a more
realistic output, I'd reccommend implementing the blocks using logic


On Wed, 5 Nov 1997, 'Bo' William Brinkman wrote:

> I have noticed that my output waveforms do not show gate delays when I
> implement them using ABEL. Is this what is supposed to happen? It seems
> strange to print out waveforms when everything magically changes at the
> right time, not showing anything of interest.
> William "Bo" Brinkman II