An ABEL source file is basically an ASCII text file written according to the requirements of the ABEL-HDL language. An ABEL source file may contain any number of modules, each with a logic description. A source file can be written using any word processor or text editor that produces ASCII files, such as the simple editor provided in the ABEL design environment.
For very complicated circuits a schematic drawing proves to be too cumbersome to create and understand. It also becomes difficult to debug the design with the wires going from one end of the schematic to another. Although we would have to learn the language syntax of ABEL but we are given more choices in terms of implementation. For insatnce we can implement our design using either using equations, truth tables, state diagrams, or a combination of the three.
To create an ABEL source we will first go to the Synario Project Navigator and start up a new project. This time, we'll declare the source as "ABEL-HDL Module" instead of "Schematic" or "Verilog Test Fixture" as shown below:
Clicking on ok, we'll be prompted for the module name, the file name, and the title of our file(see figure below). The module name supplied here would be the name of the ABEL-HDL module. The title name gives the title for the module hence we should choose a title that will be unique and descriptive and that helps us to remember the function of the module. Frequently, the module and the file name are the same. However, the file name will be appended with the .abl extension. For this project, we are going to be specifying a calender subsystem that takes as input a month and a leap-year flag and returns the number of days in the month.
Now when we click "OK" two things will happen. An ABEL file is included as a new source to our project (notice the "A" in the icon for the source file in the snapshot below) with a .abl extension and a text editor window is opened containing a template file for our module.
The Text Editor allows us to enter a textual specification of the logic we want in our module. In this case, we'll specify the month as a four-bit binary number and the leap year flag specifying whether the year is a leap year. The output is the number of days for that month.
First, we must enter a specification for the inputs and outputs.
MODULE calendar interface (m8, m4, m2, m1, leap -> d28, d29, d30, d31); TITLE 'calendar subsystem'; "Inputs m8, m4, m2, m1, leap pin; "Outputs d28, d29, d30, d31 pin istype 'com'; "Aliases month = [m8, m4, m2, m1]; days = [d28, d29, d30, d31];
The portion of the file shown above specifies the interface of the module (inputs -> outputs)and the pins. This is done with the keyword interface. The module statement is a required element of the source file. The module statement defines the beginning of a module and must be paired with an END statement that defines the module's end.The module name given determines the name of any output files created during processing by the ABEL software. The title is inserted in the source file to give a title to the module. The title statement and the description are optional. Note that in ABEL, any line that starts with a double-quote (") is a comment line (that is, the rest of the line after the quote is ignored- there is no need to close the quote). Therefore, the words "Inputs" and "Outputs" are not of any significance to ABEL. We specify the type of the outputs by using the istype keyword. In this case, we have combinational logic so our outputs are of type 'com'. We also include some aliases that group a collection of signals under one name so that we can refer to the entire group as a unit.
There are many different ways to enter a specification for the logic in many different ways. We will basically see how to write the ABEL source code for our calender system using:
To make the concept of the ABEL-HDL language more clear we will write an ABEL source for a full subtractor using inputs X, Y, and Bin and outputs Sum and Bout. For this we will open a new project and create a new ABEL source with module name and file name as "fs" , the title as 'full subtractor' and enter the following:
On compiling the ABEL source file, we obtain the fs.eq1 file which contains the following equations:
Equations:
Sum = (X & !Y & !Bin
# !X & Y & !Bin
# !X & !Y & Bin
# X & Y & Bin);
Bout = (!X & Y
# Y & Bin
# !X & Bin);
Notice that equations for Sum which we had specified in terms of X-OR gates (using $ sign) in the ABEL source has been expanded to AND, OR, and NOT gates.