USING BUSES IN VERILOG

SECTIONS

WHAT IS A BUS AND WHY IS IT USED?

Buses in Verilog serve the same purpose as do aliases in ABEL: they allow you to bundle several binary signals together into a single bus. This allows you to refer to all signals with a single name. For example, by defining a bus, you can use a single assignment using a decimal or hexadecimal number instead of several assignments to set each of the individual binary signals.

Why is this a good thing? For the same reason abstraction is good: it lets you think about the design you are working on at a high level without being distracted by the details of implementation. Instead of trying to figure out what "37" is in binary, you just say "37" and you are done. You could, of course, take the time yourself to compute "37"'s binary equivalent, but why bother with the extra work when the computer will do it for you?

HOW TO USE BUSES

The following is a simple example that shows how to use buses in Verilog. Braces { } are used to enclose a set of binary signals into a single group that can be referenced together. The following assignment statement has the same effect as assigning A3 = 0, A2 = 1, A1 = 0 and A0 = 1. 

   {A3,A2,A1,A0} = 5;
The following example is even more interesting. The + (plus) operator indicates that the signals in braces as well as the 1 are to be treated as a binary number. 
   {A3,A2,A1,A0} = {A3,A2,A1,A0} + 1;
Macros provide a convenient way to refer buses in Verilog. The following macro definition defines X to be a bus with four signals. 
   `define  X  {X3,X2,X1,X0}
After this defintion, any reference to `X is replaced with {X3,X2,X1,X0}. Note that the character before the define is not an apostraphe, but the " ` " character on the tilda key. Note also that order matters and the bits are listed from high to low. There is no semicolon at the end of the line.

Now that this macro is defined, we can use it in the following assignment. 

`X = 2;

Note once again that the character preceeding the "X" is not an apostraphe. Here you do need a semicolon to end the line. This decimal assignment is equivalent to the four boolean assignments:

X3 = 0;
X2 = 0;
X1 = 1;
X0 = 0;
And we can use the following arithmetic expression: 
`X = `X + 1;
Macros can be defined for arbitrary text, not just buses, to make Verilog programs easier to write and read.