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ABEL-HDL: The Synario tool suite supports three different hardware description languages (HDLs): ABEL, Verilog, and VHDL. ABEL is the oldest of the three and the only one designed specifically for programmable logic devices. ABEL basically provides an integrated approach to processing the design.Using ABEL, we can describe the design with equations, truth tables, state diagrams, or any combination of the three. We can also create and simulate our design without explicitly specifying a device or assigning pins. We can thus defer the implementation details and instead focus on the design itself.
Buses: Allow us to group several signals together so that the design is easier to implement, understand and debug.
Chip Report: The Chip Report describes the resource utilization of a given device based on the design which has been mapped to it. It contains: a diagram of the device showing the assignment of our pins, a description of how device resources have been allocated in realizing the design, a list of the number of product terms used per pin with names of the signals, and a list of the device's unused resources.
Clock: Sequential logic is based around using the computer's internal clock to specify when to sample inputs and when to pass outputs. For inputs, instead of constantly sampling them, as combinational logic does, sequential logic uses the clock to specify a tiny window of time in which to do the sampling. As for outputs, whereas in combinational logic any change in inputs would only have gate delays to slow it down before it could be seen on the outputs, in sequential logic outputs are only passed during a small window of time similar to input sampling, hence inputs may race through the gate levels but still not be released until the next window of time occurs.
Fuse Map: is a set of instructions created by the Chip Report for which fuses of the PLD must be blown in order to implement the design.
Fitting: is the process by which Synario maps the design to the given device. It will attempt to randomly assign the pins and nodes in the design to the physical pins and nodes in the device chosen.
Functional Simulator: The Functional Simulator is very much like the debugging process used with programming languages; whereas in the first case we step line-by-line through the code monitoring the values of variables in a numeric display, with the Simulator we step by time increments through the Test Fixture as we graphically monitor the values of the inputs, outputs, and internal signals of our design.
Finite State Machines (FSM): The finite state machines are critical for realizing the control and decision making logic in the digital syatems. The sequential logic that implements them can be done in only a fixed number of states. In the finite state machines, the outputs and the next state are determined based on the inputs and/or the present state. This distinction on how the outputs are determined gives rise to two primary types of FSMs: Moore and Mealy machines.
HDL: Hardware Design Language
Mealy Machine: The two major types of FSMs are the Moore Machine and the Mealy Machine. In the Mealy Machine, outputs are asynchronous and determined by both inputs and the current State. This means that in a State Diagram representation, the machine's outputs are indicated on the Transition Arcs rather than inside the state bubbles. Since outputs can be calculated before the new state is entered, Mealy Machines tend to be faster than their counterpart Moore Machines. The result is that many designs are diagrammed as Moore machines for convenience but actually implemented as Synchronous Mealy Machines.
Moore Machine: The two major types of FSMs are the Moore Machine and the Mealy Machine. In a Moore Machine, the machine's outputs are synchronous and determined solely by the current State. This means that in a State Diagram representation, the machine's outputs are indicated inside the state bubbles rather than on the Transition Arcs. Since outputs cannot be determined until after a given state has been entered, Moore machines tend to be slower than their counterpart Mealy machines, the result being that many designs are diagrammed as Moore machines for convenience but actually implemented as Synchronous Mealy Machines.
Node: A node is basically an output whose value is never passed, but only used internally within a module.
PLD: Programmable Logic Devices
Schematic: A schematic is a drawing that represents all or part of an electronic circuit.
State: Sequential machines are often easy to consider as FSMs, which are a collection of States which the machine passes through via a State Diagram.
State Diagram: A state diagram is an efficient tool for representing FSMs. States are represented as bubbles and transitions between states are represented as Transition Arcs.
Synario: Synario is a tool suite which provides an integrated environment for both designing hardware systems and testing those designs through software simulation. Designs can be constructed utilizing either stand-alone or a combination of schematics and HDLs (hardeware design languages) such as ABEL. Through software simulation, errors in design can be detected early and corrected without a design's having ever been implemented in physical form, thus preventing the wasted time and expense of physically building a faulty design. Synario is run on WindowsNT 4.0.
Synchronous Mealy Machine: A Mealy Machine with registered outputs, the Synchronous Mealy Machine combines the best aspects of the Mealy Machine with those of the Moore Machine and is the most commonly used method of implementating an FSM. Most machines are diagrammed as Moore Machines with the understanding that the implementer will actually apply the output value shown inside the State bubble and to each Transition Arc leading into the given state.
Test Fixture: A Verilog Test Fixture is a testing file with .TF extension. The Test fixture file contains test fixtures for a design using ABEL-HDL and schematics. This file is usually a just a skeleton of what can be tested
Transition Arc: Used in a State Diagram, a Transition Arc shows a one-way path between two States.
Virtual Device: This is the default device used by Synario when a design is not mapped explicitly to any specific programmable logic device. This is Synario's way of allowing us to create our designs without worrying at all about what hardware might be used to actually implement the designs in physical form.