We will be using the Intel PCs located in Sieg 232. Please do not eat or drink in the laboratory, and respect both the equipment and your fellow students.
These machines were donated to the department by Intel Corporation of Hillsboro, OR.
We will be using DesignWorks, from Capilano Computing, for schematic capture and simulation. DesignWorks contains limited Verilog support, that we will use later in the quarter. With DesignWorks and a word processor, you can draw and simulate your design, and incorporate the schematic and simulator output into your assignment write-ups.
John Naegle has created a DesignWorks tip page located here. Check it out—it will save you a lot of time.
DesignWorks has several reference manuals viewable with Adobe Acrobat Reader, (also available on the CSE department's instructional PCs):
Schematic
Capture (the main manual)
Simulator
Verilog
Sequential Verilog Slides
(ppt format) from week 8 section.
Verilog Web sites. Books about Verilog tend to be expensive, but here are some web pages that may be helpful.
Want to run at home? Capilano has a free evaluation version called Design Works Lite. There is also a student version called LogicWorks 4, that is upward compatible to Design Works. It is not free, but there is an excellent new book about it that includes the software on a CD. (At present [1/3/99] I don't know enough about these products to say how many of our assignments they could be used for -- sorry.)
All the machines in the lab have Microsoft Office and other application software installed. Unless your handwriting is exceedingly legible, please use software tools to write up your assignments.
The MSOffice software was donated to the department by Microsoft Corporation of Redmond, WA.