Today: Verilog and Sequential Logic

5/11/99


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Table of Contents

Today: Verilog and Sequential Logic

Incorrect Flip-flop in Verilog

Correct Flip-flop in Verilog

More Flip-flops

Verilog Implementation of a Counter (State Machine)

Verilog BCD Counter Example

$display and $time statements

Blocking and Non-Blocking Assignments

RTL Assignment

 Author: Gaetano Borriello

Email: cse370-webmaster@cs.washington.edu

Home Page: http://www.cs.washington.edu/education/courses/cse370/CurrentQtr/