Table of Contents
Today
Timing in DesignWorks: Generating useful output
Timing in DesignWorks: Gate Delay Properties
Notes on Multiplexers as general-purpose logic
Notes on Multiplexers as general-purpose logic (cont’d)
Demultiplexers versus Decoders
BCD to 7-segment display controller
Formalize the problem
Implementation as minimized SOP
Implementation as minimized SOP (cont'd)
Hardware Demonstration: Protoboard Layout
Hardware Demonstration: TTL Parts
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Author: Jeffrey Hightower
Email: cse370-webmaster@cs.washington.edu
Home Page: http://www.cs.washington.edu/education/courses/cse370/CurrentQtr/
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