S=0: Hold (NOP) S=1: Load input S=2: Clear S=3: Complement contents S=4: Shift right 1 S=5: Rotate right 1 S=6: Shift left 1 S=7: Rotate left 1
In this homework, you will learn to use
statements to show what's going on inside a Verilog module.
Display statements are documented in the LVM (Verilog) manual
on page 56. You have to put them inside an
block. In each of your Verilog modules, you should display
vectors which correspond to your input and output ports, using the
%h specifier. Ports which aren't part of a vector
(such as a carry out bit) should also be displayed individually.
$display statement at the bottom of your
always block. (Create one if you don't already have
one.) To show that you have this working, turn in a screen
shot of the window which shows this output.
For the shift register, set the data inputs to
11100111; then start S at 0. Increment S every
third clock cycle until you reach 7, then decrement it every
second clock cycle until you're back at 0. The entire sequence
For the Gray counter, start with it disabled. Reset it (leaving it disabled; it should reset even while disabled) for two cycles, then take it out of reset but let it stay disabled for two cycles. Enable it and let it run for ten (10) cycles. Reset it (but leave it enabled) for two cycles, then take it out or reset for two more cycles.
For the dual-input register, come up with your own interesting test cases. For the non-Verilog version (problem 2), you should turn in a clearly labeled waveform.
Of course, you should turn in printouts of all of your circuits, subcircuits, and verilog models. Remember that printers can print duplex (2-sided) so save a tree if possible.
Finally, remember to create and save library parts for everything you build in this assignment. It is very likely that you will be asked to use these parts as part of another design in subsequent assignments.