## CSE370 Assignment 7

### Distributed: 7 May 1999 Due: 14 May 1999

1. Katz, Chapter 4 (pp. 194-202).
2. Katz, Chapter 7 (pp. 337-345, 352-356).
3. Katz, Chapter 8 (pp. 383-395).

#### Exercises:

1. In Verilog, design an 8-bit shift register with 8 data inputs D7...D0 (high-order to low-order) and 3-bits of control inputs (S2,S1,S0) which define the operation of the shift register as follows (for the two shift operations, you should shift in 0 on the ends).
```S=0: Hold (NOP)
S=2: Clear
S=3: Complement contents
S=4: Shift right 1
S=5: Rotate right 1
S=6: Shift left 1
S=7: Rotate left 1```
2. Using just the basic D flip-flop and combinational logic, design a 4-bit register with a load input (load) and an input select (sel) to choose which of two possible 4-bit inputs (A or B) to load.  Do this with a DesignWorks schematic.
3. Repeat the problem above using Verilog and making the register be 16 bits wide instead of 4.  Create a library block for this register.
4. Create a counter that counts in Gray code (000, 001, 011, 010, 110, 111, 101, 100, 000, ... ). It should have a reset signal that sets it to 110 and an enable input that stops the counter (holds the current value) when low. Do this in Verilog using a "case" statement. (Hint: Follow good design practices and layout a transition table and/or state diagram before doing the Verilog implementation)

#### What to turn in:

In this homework, you will learn to use `\$display` statements to show what's going on inside a Verilog module. Display statements are documented in the LVM (Verilog) manual on page 56. You have to put them inside an `always` block. In each of your Verilog modules, you should display vectors which correspond to your input and output ports, using the `%h` specifier. Ports which aren't part of a vector (such as a carry out bit) should also be displayed individually. Put this `\$display` statement at the bottom of your `always` block. (Create one if you don't already have one.) To show that you have this working, turn in a screen shot of the window which shows this output.

For the shift register, set the data inputs to `11100111`; then start S at 0. Increment S every third clock cycle until you reach 7, then decrement it every second clock cycle until you're back at 0. The entire sequence is 00011122233344455566677766554433221100.

For the Gray counter, start with it disabled. Reset it (leaving it disabled; it should reset even while disabled) for two cycles, then take it out of reset but let it stay disabled for two cycles. Enable it and let it run for ten (10) cycles. Reset it (but leave it enabled) for two cycles, then take it out or reset for two more cycles.

For the dual-input register, come up with your own interesting test cases. For the non-Verilog version (problem 2), you should turn in a clearly labeled waveform.

Of course, you should turn in printouts of all of your circuits, subcircuits, and verilog models. Remember that printers can print duplex (2-sided) so save a tree if possible.

Finally, remember to create and save library parts for everything you build in this assignment. It is very likely that you will be asked to use these parts as part of another design in subsequent assignments.

#### Rationale:

• To develop an understanding of basic sequential logic elements.
• To be able to design simple sequential logic circuits such as registers and counters.
• To use a hardware description language for the specification of sequential logic.

Comments to: cse370-webmaster@cs.washington.edu (Last Update: 05/24/99)