CSE 370 Solution Set #6
Spring 1999

Total Points 20

1) 2 Points:
To get full credit you needed to demonstrate somehow with simulation that your adder works. This is just one verilog example but there were many ways to do this, some better than others...

module Adder4bit(A0, A1, A2, A3, B0, B1, B2, B3, Cin, S0, S1, S2, S3, Cout);
input  A0;
input  A1;
input  A2;
input  A3;
input  B0;
input  B1;
input  B2;
input  B3;
input  Cin;
output S0;
output S1;
output S2;
output S3;
output Cout;

reg S0, S1, S2, S3, Cout;
reg[4:0] A;
assign A = {1'B0, A3, A2, A1, A0};
reg[4:0] B;
assign B = {1'B0, B3, B2, B1, B0};
reg[4:0] Sum;

assign Sum = A + B + Cin;
assign Cout = Sum[4];
assign S3 = Sum[3];
assign S2 = Sum[2];
assign S1 = Sum[1];
assign S0 = Sum[0];

endmodule

2) 5 Point:
Here's a possible schematic for the 8-bit carry-select adder. Again to get full credit your solution needed to demonstrate that the adder works correctly.

3) 3 Point:
Here's a possible verilog solution for the calendar subsystem:

module Calendar(month3,month2,month1,month0, leap_flag, d28, d29, d30, d31);
input  month3, month2, month1, month0;
input  leap_flag;
output d28, d29, d30, d31;

reg d28, d29, d30, d31;

assign d28 = (~month3 & ~month2 & month1 & ~month0 & ~leap_flag);
assign d29 = (~month3 & ~month2 & month1 & ~month0 & leap_flag);
assign d30 = (~month3 & month2 & ~month0) | (month3 & month0);
assign d31= (~month3 & month0) | (month3 & ~month0);

endmodule

4) 4 Points:
Here's a verilog 4-bit ALU slice:

module ALU4bit(A3, A2, A1, A0, B3, B2, B1, B0, Cin, Ctr2, Ctr1, Ctr0, S3, S2, S1, S0, Cout, Zero, Neg);
input  A3, A2, A1, A0;
input  B3, B2, B1, B0;
input  Cin;
input Ctr2, Ctr1, Ctr0;
output S3, S2, S1, S0;
output Cout;
output Zero;
output Neg;

reg S3, S2, S1, S0;
reg Cout;
reg Zero;
reg Neg;
reg [4:0] A, B, R;
reg [2:0] Ctrl;

assign A = {1'b0, A3, A2, A1, A0};
assign B = {1'b0, B3, B2, B1, B0};
assign Ctrl = {Ctr2, Ctr1, Ctr0};

always@(A or B or Ctrl or Cin) begin

case(Ctrl)

3'b000: R = A + B + {4'b0000, Cin};
3'b001: R = A + (B ^ 5'b01111) + 1;
3'b010: R = A + {5'b00001};
3'b011: R = A & B;
3'b100: R = A | B;
3'b101: R = A ^ (~B);
3'b110: R = A;
3'b111: R = B;

endcase
end

assign Cout = R[4];
assign Neg = R[3];
assign S3 = R[3];
assign S2 = R[2];
assign S1 = R[1];
assign S0 = R[0];
assign Zero = ~(R[0] | R[1] | R[2] | R[3]);

endmodule

Here's a good example of the entire 16-bit ALU. To get full credit you needed to correctly show that your ALU performed the 8 test operations on the homework:

5) 4 Points:
Here's the timing diagrams for Katz 6.11. For part (b) we accepted a couple interpretations since the master/slave flip flop is not well defined in the book. The interpretation shown below is where the master/slave flip flop samples the entire period while the clock is high (exhibits 1s-catching) but does not show that output until the falling edge of the clock.

6) 2 Points:
The truth table for implementing a D flip-flop from a T flip-flop. Remember D is our input and we're trying to map our D input to the toggle flip-flop input T based on what we want NextQ to be:

 D CurrentQ | NextQ T 0 0 | 0 0 0 1 | 0 1 1 0 | 1 1 1 1 | 1 0

From the table you see that T = D xor CurrentQ

Here's the schematic for a D flip-flop from a T flip-flop: