## CSE370 Assignment 6

### Distributed: 30 April 1999 Due: 7 May 1999

1. Katz, Chapter 6 (pp. 282-313).
2. Katz, Chapter 7 (pp. 329-337).

#### Exercises:

1. Construct a Verilog model for a 4-bit adder. Use the Verilog "+" operator to implement addition. Verify it using the same examples as for the last assignment. Make sure that your module includes a carry-out output for use in the next problem. Turn in the Verilog source for your module and the simulation waveforms.
2. Design a 8-bit carry-select adder for unsigned numbers. It should be designed hierarchically at the schematic diagram level and include 3 instances of the Verilog module you defined in the previous problem. Verify its operation for "11111111" + "00000001". Turn in the schematic and simulation waveform.
3. Implement the calendar subsystem we've done in class using Verilog. Create a module whose inputs are month and leap_flag and whose outputs are d28, d29, d30, and d31. Turn in your Verilog source.
4. Design a 16-bit ALU. Numbers will be represented in 2s complement form. You should compose the ALU from four identical instantiations of a 4-bit slice. Use a schematic to compose the four into a single ALU and add any additional logic you may require. Use your adder for the first exercise as a starting point.

The ALU has control signals that specify one of eight functions (add, subtract, increment A, logical AND, logical OR, logical XNOR, pass A, and pass B). The data input signals are labelled a15 to a0 and b15 to b0 (with a15 and b15 being the high-order bits). The data output signals should be labelled c15 to c0, there are two other outputs: neg, and zero which are asserted when the output is negative or equal to zero, respectively. These two outputs should be valid for all operations regardless of whether they are arithmetic or logical operations.

Turn in your schematics, Verilog files, and simulation waveforms for the following cases:

1. add, -1 and 2 to yield 1
2. sub, 7 and 8 to yield -1
3. incA, -1 and 12 to yield 0
4. and, 7 and 5 to yield 5
5. or, 6 and 5 to yield 7
6. xnor, 5 and 4 to yield -2
7. passA, -128 and 65 to yield -128
8. passB, 5 and 10 to yield 10

5. Katz exercise 6.11.
6. Katz exercise 6.17.

#### Suggested alternative submission

Instead of turning in waveforms for this week's DesignWorks problems, you may instead turn in screen shots of the DVM pop-up window to demonstrate that you have Verilog modules which work correctly. This is an optional alternative, not an additional requirement; however, note that if you choose to turn in waveforms instead, you must clearly label the required transitions, and make sure they're zoomed appropriately.

If you choose to do this, you need to first open up the DVM pop-up for each Verilog module. Then click on the ">>" button in each DVM pop-up to show all of your internal variables. (If this fails, save everything, and quit and restart DesignWorks.)

For the 4-bit and 8-bit adder, you then need to show your ports as well (see the DVM Options menu). Also, you need to show current values for your circuit before and after the transitions given.

For the 16-bit ALU test cases 2-8, you only need to show the first and last bit slice, not the middle two.

Use Alt-PrintScreen to take a snapshot of the current window, or Ctl-PrintScreen to grab the entire screen. Now your image is on the clipboard. How you do the rest is up to you, but you should clearly label everything with which submodule and which test case it represents.

#### Rationale:

• To lean the use of a hardware description language to design circuit blocks.
• To reinforce speed/area tradeoffs in combinational logic design.
• To gain facility with hierarchical design and the tradeoffs inherent in creating multi-purpose components.
• To begin understanding the basic building blocks of sequential circuits.

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