CSE370 Assignment 5

Distributed: 23 April 1999
Due: 30 April 1999

Reading:

1. Katz, Chapter 4 (pp. 207-224).
2. Katz, Chapter 5 (pp. 240-266).

Exercises:

1. Katz exercise 4.18 (a,b).
2. Katz exercise 4.21 (a,b). In addition, implement (c) using an appropriately sized PLA (minimum number of product terms and no extra inputs or outputs) similar to the one in Fig. 4.5.
3. Implement a combinational logic circuit that converts a 5-bit sign and magnitude number into the corresponding 4-bit 2s complement number. The circuit should have an additional "error" output when the conversion can not be done becuase the number is out of range. Make sure to exploit don't cares in your solution (i.e., when there is an error we do not care what the converted number is). Draw an input/output conversion truth table, intermediate K-maps (yes, I know they will be 5-variables), and your minimized two-level logic description. Implement your circuit using the 16H8 PAL of Fig. 4.72 (i.e., print out the figure and places "x"s where you want connections made in the AND plane. Ignore the first product term in each group that goes to the tri-state buffer (triangle) after the OR gate.
4. Draw schematics for two versions of a full-adder in DesignWorks. One should be done using a half-adder as a sub-block and another without sub-blocks. Make sure to read Chapters 7 and 8 of the DesignWorks manual that describe how to create your own symbols. Turn in the schematics for each type of full-adder and for the half-adder symbol. Simulate your schematics. Verify that your designs are correct by trying all 8 input combinations in each case. Turn in the timing waveforms as well.
5. Construct a 4-bit ripple-carry adder using the full-adder implementation from the previous problem (use the one built using the half-adder as a sub-block). Turn in the schematic. To verify your design, you may want to use "Hex Keyboard" symbol in the "Primio" library to make it easier to input a 4-bit number. Turn in the timing waveforms showing what happens when you have "1111" and "0000" as the numbers to be added and you change the "0000" to "0001". How long does it take the sum to get to the right value? Repeat this experiment starting with "1010" and "0000" and changing the "0000" to "0101".
6. Construct a 4-bit carry-lookahead adder using the same full-adder implementation as the previous problem. And repeat the experiments above. How much faster is the carry-lookahead adder?
7. Construct an 8-bit carry-select adder from the 4-bit carry-lookahead adders of the previous problem. Turn in DesignWorks schematics and verify that your 8-bit adder works correctly (you do not need to turn in any timing waveforms for this problem).

Materials:

• A printable PAL schematic (pal.jpg or pal.pdf) from Katz page 217.

Rationale:

• To practice how to convert word problems into a combinational logic formulation.
• To understand the implementation of addition in combinational logic networks.
• To compose hierarchical combinational circuits.