| Assignment | Date Distributed | Date Due | Annotated Solutions |
| Assignment 1 | 9/27/99 | 10/4/99 | Solution 1 |
| Assignment 2 (pdf) | 10/4/99 | 10/11/99 |
Solution 2
Design Works Files for Question 3a(Circuit) |
| Assignment 3 | 10/11/99 | 10/18/99 | Solution 3 |
| Assignment 4 PDF or Web | 10/18/99 | 10/27/99 | |
| Assignment 5 PDF or Web | 11/1/99 | 11/8/99 | Solution 5 |
| Assignment 6 PDF or Web | 11/8/99 | 11/15/99 | Solution 6 in HTML or PDF |
| Assingment 7 in PDF or Web | 11/17/99 | 11/24/99 | Solution 7 in PDF |
| Assignment 8 in PDF
or Web
ALU with SHR modification ALU with SHR w/ bug fixes (shifting and F7 port direction) Verilog File for Decoder inside ALUDP in above DW file Tester DW file with Verilog File Note: Verilog files included for reference. You should be able to use the tester and the ALU without reloading the Verilog into Design Works |
11/23/99 | 12/9/99
noon |
DW Solution to Problem 4 |