Table of Contents
Combinational versus sequential logic
Basic memory element: D flip-flop
D flip-flop timing
Building Synchronous Circuits
Cascading D flip-flops
Timing Requirements
Clock skew
Metastability and asynchronous inputs
Synchronizer failure
Minimizing synchronizer failures
Handling asynchronous inputs
Handling asynchronous inputs (cont'd)
Registers
Shift registers
Universal shift register
Design of universal shift register
Shift-register applications
Finite state machines
Some examples: Ring and Johnson counters
Counter design procedure
Example: Design a 3-bit up counter
Example: Design a 3-bit up counter (con’t)
Example: Design a 3-bit up counter (con’t)
Another example: A 5-state counter
5-state counter design (con’t)
5-state counter design (con’t)
Self-starting counters
Self-starting counters (cont'd)
Binary counter
Four-bit binary synchronous up-counter
Offset counters
Finite state machines
Finite state machine representations
State machine model
FSM design procedure
FSM design procedure
Moore versus Mealy machines
Specifying outputs for a Moore machine
Specifying outputs for a Mealy machine
Comparison of Mealy and Moore machines
Mealy and Moore example
Example: serial adder
Example: vending machine
Example: vending machine (state diagram)
Vending machine (symbolic state transition table)
Example: vending machine (state encoding)
Vending machine (two-level logic implementation)
FSM implementation
Synchronous versus asynchronous FSMs
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