CSE370 Assignment 9

Distributed: March 6, 1998
Due: March 13, 1998

Reading:

Katz: Chapter 6.3
Katz: Chapter 7.2-7.4

Project Completion

In this assignment, you will complete the implementation of our processor. Attached is an example schematic for this processor along with the test fixture that you should use. You will find this example in the folder cse370\Winter98\Project\ This folder contains both the schematic and the test fixture. Note that it also contains the .SYM files for the symbols - you can use these symbols if you use the same signal names that I did. You can open this project and view the schematic and test fixture, but it will complain that none of the other source files are there.

The test fixture implements both the instruction memory and the data memory. This test fixture initializes the data memory and the instruction memory and then runs 100 clock cycles (which is long enough for your programs). When it's done, it prints out the first few locations in the data memory. Don't change the test fixture except to try out different programs!

The test fixture contains a simple program that uses all but a few of the instructions. Use can this program to test and debug your processor. Feel free to write new programs and mail them to the class. We will give you a program next week that tests all the instructions.

Extra Credit

There are lots of possibilities for extra credit. Here are a few:
  1. Our processor takes two cycles to do each instruction. Change the processor to perform an instruction every cycle. Of course, it still takes two cycles to perform one instruction, but we will fetch the next instruction while we are executing the current one.

  2. A lot happens during the execute cycle of the processor: The register file reads, the ALU executes and the result is written back to the register file. Usually the ALU is not fast enough to have the result ready in time to write back to the register file.

    Change the processor by adding a register on the output of the ALU so that the result is saved in this register and then written back on the next clock cycle. Of course, we still want to execute an instruction every cycle, so this will require some fancy footwork to make this work. (Note that it now take three cycles to perform one instruction, but we complete an instruction every cycle because of pipelining.)

  3. There are a lot of things that our instruction set cannot handle. For example, how would you implement a program that uses a vector? Extend the instruction set so that you could write a program that adds together the first N values in the memory.
Processor Description

The processor uses two memories, instruction memory, which contains 32 8-bit instructions, and data memory, which contains 16 8-bit words. The processor also has a register file with 4 registers. This processor has the following instruction set: 

Mnemonic    Format         Description
--------------------------------------------
LOAD        00 AAAA RR    Load register RR with data at address AAAA
STORE       01 AAAA RR    Store register RR to address AAAA
JMP         100  AAAAA    Jump to instruction at address AAAAA
JMPZ        101  AAAAA    Jump to address AAAAA if the last ALU result was zero
ADD         1100 SS DD    Add register SS to register DD
SUB         1101 SS DD    Subtract register SS from register DD
CLR         111000  RR    Clear register RR
INC         111001  RR    Increment register RR
DEC         111010  RR    Decrement register RR
HALT        11111111      Halt execution
The processor uses two registers to help execute the program, the program counter (PC) and the instruction register (IR). When the processor starts, the PC is set to 0. The processor then executes one instruction at a time, using two clock cycles, as follows:

In the first clock cycle, the instruction memory is read using the PC as the address. This instruction is stored in the IR and the PC is incremented.

In the second clock cycle, the processor executes the instruction in the IR. It does this by asserting the appropriate control signals to the processor datapath (ALU, registers and memories) so that the right thing happens on the next clock tick.

Comments to: cse370-webmaster@cs.washington.edu (Last Update: )